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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpDiv_tb.v] - Diff between revs 11 and 14

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Rev 11 Rev 14
Line 52... Line 52...
reg [3:0] state;
reg [3:0] state;
 
 
initial begin
initial begin
        rst = 1'b0;
        rst = 1'b0;
        clk = 1'b0;
        clk = 1'b0;
        adr = 0;
        adr = 13'd0;
        $readmemh("c:/cores5/ft64/trunk/rtl/fpUnit/fpDiv_tv.txt", mem);
        $readmemh("d:/cores5/ft64/v5/rtl/fpUnit/fpDiv_tv.txt", mem);
        $readmemh("c:/cores5/ft64/trunk/rtl/fpUnit/fpDiv_tvd.txt", memd);
        $readmemh("d:/cores5/ft64/v5/rtl/fpUnit/fpDiv_tvd.txt", memd);
        #20 rst = 1;
        #20 rst = 1'd1;
        #50 rst = 0;
        #50 rst = 1'd0;
end
end
 
 
always #5
always #10
        clk = ~clk;
        clk = ~clk;
 
 
always @(posedge clk)
always @(posedge clk)
if (rst) begin
if (rst) begin
        adr = 0;
        adr = 13'd0;
        state <= 1;
        state <= 4'd4;
end
end
else
else
begin
begin
        ld <= 1'b0;
        ld <= 1'b0;
case(state)
case(state)
Line 78... Line 78...
                a <= mem[adr][31: 0];
                a <= mem[adr][31: 0];
                b <= mem[adr][63:32];
                b <= mem[adr][63:32];
                ad <= memd[adr][63:0];
                ad <= memd[adr][63:0];
                bd <= memd[adr][127:64];
                bd <= memd[adr][127:64];
                ld <= 1'b1;
                ld <= 1'b1;
                state <= 2;
                state <= 4'd2;
        end
        end
4'd2:
4'd2:
 
                state <= 4'd3;
 
4'd3:
        if (done) begin
        if (done) begin
                memo[adr] <= {o,b,a};
                memo[adr] <= {o,b,a};
                memdo[adr] <= {od,bd,ad};
                memdo[adr] <= {od,bd,ad};
                adr <= adr + 1;
                adr <= adr + 4'd1;
                if (adr==8191) begin
                if (adr==13'd8191) begin
                        $writememh("c:/cores5/ft64/trunk/rtl/fpUnit/fpDiv_tvo.txt", memo);
                        $writememh("d:/cores5/ft64/v5/rtl/fpUnit/fpDiv_tvo.txt", memo);
                        $writememh("c:/cores5/ft64/trunk/rtl/fpUnit/fpDiv_tvdo.txt", memdo);
                        $writememh("d:/cores5/ft64/v5/rtl/fpUnit/fpDiv_tvdo.txt", memdo);
                        $finish;
                        $finish;
                end
                end
                state <= 3;
                state <= 4'd4;
        end
        end
4'd3:   state <= 4;
4'd4:   state <= 4'd5;
4'd4:   state <= 5;
 
4'd5:   state <= 1;
4'd5:   state <= 1;
endcase
endcase
end
end
 
 
fpDivnr #(32) u1 (clk, 1'b1, ld, a, b, o, 3'b000);//, sign_exe, inf, overflow, underflow);
fpDivnr #(32) u1 (rst, clk, 1'b1, ld, 1'b0, a, b, o, 3'b000);//, sign_exe, inf, overflow, underflow);
fpDivnr #(64) u2 (clk, 1'b1, ld, ad, bd, od, 3'b000, done);//, sign_exe, inf, overflow, underflow);
fpDivnr #(64) u2 (rst, clk, 1'b1, ld, 1'b0, ad, bd, od, 3'b000, done);//, sign_exe, inf, overflow, underflow);
 
 
endmodule
endmodule
 
 
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