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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpFMA.v] - Diff between revs 23 and 25

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Rev 23 Rev 25
Line 109... Line 109... 
fpDecompReg #(WID) u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb1), .exp(xb1), .fract(fractb1), .xz(b_dn1), .vz(bz1), .inf(bInf1), .nan(bNan1) );
 
fpDecompReg #(WID) u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb1), .exp(xb1), .fract(fractb1), .xz(b_dn1), .vz(bz1), .inf(bInf1), .nan(bNan1) );
 
fpDecompReg #(WID) u1c (.clk(clk), .ce(ce), .i(c), .sgn(sc1), .exp(xc1), .fract(fractc1), .xz(c_dn1), .vz(cz1), .inf(cInf1), .nan(cNan1) );
 
fpDecompReg #(WID) u1c (.clk(clk), .ce(ce), .i(c), .sgn(sc1), .exp(xc1), .fract(fractc1), .xz(c_dn1), .vz(cz1), .inf(cInf1), .nan(cNan1) );
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) op1 <= op;
 
        if (ce) op1 <= op;
 
assign xcInf1 = &xc1;
 
 
 
 
 
 
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
// Clock #2
 
// Clock #2
 
// Compute the sum of the exponents.
 
// Compute the sum of the exponents.
 
// correct the exponent for denormalized operands
 
// correct the exponent for denormalized operands
Line 124... Line 123... 
 
 
 
 
reg abz2;
 
reg abz2;
 
reg [EMSB+2:0] ex2;
 
reg [EMSB+2:0] ex2;
 
reg [EMSB:0] xc2;
 
reg [EMSB:0] xc2;
 
reg realOp2;
 
reg realOp2;
 
 
 
reg xcInf2;
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) abz2 <= az1|bz1;
 
        if (ce) abz2 <= az1|bz1;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) ex2 <= (xa1|a_dn1) + (xb1|b_dn1) - bias;
 
        if (ce) ex2 <= (xa1|a_dn1) + (xb1|b_dn1) - bias;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) xc2 <= (xc1|c_dn1);
 
        if (ce) xc2 <= (xc1|c_dn1);
 
 
 
always @(posedge clk)
 
 
 
        if (ce) xcInf2 = &xc1;
 
 
 
 
 
// Figure out which operation is really needed an add or
 
// Figure out which operation is really needed an add or
 
// subtract ?
 
// subtract ?
 
// If the signs are the same, use the orignal op,
 
// If the signs are the same, use the orignal op,
 
// otherwise flip the operation
 
// otherwise flip the operation
Line 426... Line 428... 
                5'b0001?:       ex6 <= infXp;   // result overflow
 
                5'b0001?:       ex6 <= infXp;   // result overflow
 
                5'b00001:       ex6 <= ex5[EMSB:0];//0;          // underflow
 
                5'b00001:       ex6 <= ex5[EMSB:0];//0;          // underflow
 
                default:        ex6 <= ex5[EMSB:0];      // situation normal
 
                default:        ex6 <= ex5[EMSB:0];      // situation normal
 
                endcase
 
                endcase
 
 
 
 
 
always @(posedge clk)
 
 
 
        if (ce)
 
 
 
                casez({qNaNOut5|aNan5|bNan5,aInf5,bInf5,over5,under5})
 
 
 
                5'b1????:       exinf6 <= 1'b1; // qNaN - infinity * zero
 
 
 
                5'b01???:       exinf6 <= 1'b1; // 'a' infinite
 
 
 
                5'b001??:       exinf6 <= 1'b1; // 'b' infinite
 
 
 
                5'b0001?:       exinf6 <= 1'b1; // result overflow
 
 
 
                5'b00001:       exinf6 <= |ex5[EMSB:0];//0;              // underflow
 
 
 
                default:        exinf6 <= |ex5[EMSB:0];  // situation normal
 
 
 
                endcase
 
 
 
 
 
 
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
// Clock #7
 
// Clock #7
 
// - prep for addition, determine greater operand
 
// - prep for addition, determine greater operand
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
reg ex_gt_xc7;
 
reg ex_gt_xc7;
 
reg xeq7;
 
reg xeq7;
 
reg ma_gt_mc7;
 
reg ma_gt_mc7;
 
reg meq7;
 
reg meq7;
 
reg exinf7;
 
 
 
wire az7, bz7, cz7;
 
wire az7, bz7, cz7;
 
wire realOp7;
 
wire realOp7;
 
 
 
 
 
always @(posedge clk)
 
 
 
        if (ce) exinf7 <= exinf6;
 
 
 
// which has greater magnitude ? Used for sign calc
 
// which has greater magnitude ? Used for sign calc
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) ex_gt_xc7 <= (ex6 > xc6) && !under6;
 
        if (ce) ex_gt_xc7 <= (ex6 > xc6) && !under6;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) xeq7 <= (ex6==xc6) && !under6;
 
        if (ce) xeq7 <= (ex6==xc6) && !under6;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) ma_gt_mc7 <= mo6 > {fractc6,{FMSB+1{1'b0}}};
 
        if (ce) ma_gt_mc7 <= mo6 > {fractc6,{FMSB+1{1'b0}}};
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) meq7 <= mo6 == {fractc6,{FMSB+1{1'b0}}};
 
        if (ce) meq7 <= mo6 == {fractc6,{FMSB+1{1'b0}}};
 
vtdl u71 (.clk(clk), .ce(ce), .a(4'd5), .d(az1), .q(az7));
 
vtdl #(1) u71 (.clk(clk), .ce(ce), .a(4'd5), .d(az1), .q(az7));
 
vtdl u72 (.clk(clk), .ce(ce), .a(4'd5), .d(bz1), .q(bz7));
 
vtdl #(1) u72 (.clk(clk), .ce(ce), .a(4'd5), .d(bz1), .q(bz7));
 
vtdl u73 (.clk(clk), .ce(ce), .a(4'd5), .d(cz1), .q(cz7));
 
vtdl #(1) u73 (.clk(clk), .ce(ce), .a(4'd5), .d(cz1), .q(cz7));
 
vtdl u74 (.clk(clk), .ce(ce), .a(4'd4), .d(realOp2), .q(realOp7));
 
vtdl #(1) u74 (.clk(clk), .ce(ce), .a(4'd4), .d(realOp2), .q(realOp7));
 
 
 
 
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
// Clock #8
 
// Clock #8
 
// - prep for addition, determine greater operand
 
// - prep for addition, determine greater operand
 
// - determine if result will be zero
 
// - determine if result will be zero
Line 476... Line 464... 
reg a_gt_b8;
 
reg a_gt_b8;
 
reg resZero8;
 
reg resZero8;
 
reg ex_gt_xc8;
 
reg ex_gt_xc8;
 
wire [EMSB:0] ex8;
 
wire [EMSB:0] ex8;
 
wire [EMSB:0] xc8;
 
wire [EMSB:0] xc8;
 
reg exinf8;
 
 
 
wire xcInf8;
 
wire xcInf8;
 
wire [2:0] rm8;
 
wire [2:0] rm8;
 
wire op8;
 
wire op8;
 
wire sa8, sb8, sc8;
 
wire sa8, sb8, sc8;
 
 
 
 
 
delay2 #(EMSB+1) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8));
 
delay2 #(EMSB+1) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8));
 
delay2 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xc6), .o(xc8));
 
delay2 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xc6), .o(xc8));
 
vtdl u83 (.clk(clk), .ce(ce), .a(4'd6), .d(xcInf1), .q(xcInf8));
 
vtdl #(1) u83 (.clk(clk), .ce(ce), .a(4'd5), .d(xcInf2), .q(xcInf8));
 
vtdl #(3) u84 (.clk(clk), .ce(ce), .a(4'd7), .d(rm), .q(rm8));
 
vtdl #(3) u84 (.clk(clk), .ce(ce), .a(4'd7), .d(rm), .q(rm8));
 
vtdl u85 (.clk(clk), .ce(ce), .a(4'd6), .d(op1), .q(op8));
 
vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd6), .d(op1), .q(op8));
 
vtdl u86 (.clk(clk), .ce(ce), .a(4'd7), .d(sa1 ^ sb1), .q(sa8));
 
vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd7), .d(sa1 ^ sb1), .q(sa8));
 
vtdl u87 (.clk(clk), .ce(ce), .a(4'd7), .d(sc1), .q(sc8));
 
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd7), .d(sc1), .q(sc8));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) exinf8 <= exinf7;
 
 
 
always @(posedge clk)
 
 
 
        if (ce) ex_gt_xc8 <= ex_gt_xc7;
 
        if (ce) ex_gt_xc8 <= ex_gt_xc7;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce)
 
        if (ce)
 
                a_gt_b8 <= ex_gt_xc7 || (xeq7 && ma_gt_mc7);
 
                a_gt_b8 <= ex_gt_xc7 || (xeq7 && ma_gt_mc7);
 
 
 
 
Line 535... Line 520... 
delay3 #(FX+1) u93 (.clk(clk), .ce(ce), .i(mo6), .o(mo9));
 
delay3 #(FX+1) u93 (.clk(clk), .ce(ce), .i(mo6), .o(mo9));
 
delay3 #(FMSB+2) u94 (.clk(clk), .ce(ce), .i(fractc6), .o(fractc9));
 
delay3 #(FMSB+2) u94 (.clk(clk), .ce(ce), .i(fractc6), .o(fractc9));
 
delay3 u95 (.clk(clk), .ce(ce), .i(under6), .o(under9));
 
delay3 u95 (.clk(clk), .ce(ce), .i(under6), .o(under9));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) ex9 <= (exinf8&xcInf8) ? ex8 : resZero8 ? 0 : ex_gt_xc8 ? ex8 : xc8;
 
        if (ce) ex9 <= resZero8 ? 0 : ex_gt_xc8 ? ex8 : xc8;
 
 
 
 
 
// Compute output sign
 
// Compute output sign
 
always @*
 
always @(posedge clk)
 
 
 
        if (ce)
 
        case ({resZero8,sa8,op8,sc8})   // synopsys full_case parallel_case
 
        case ({resZero8,sa8,op8,sc8})   // synopsys full_case parallel_case
 
        4'b0000: so9 <= 0;                       // + + + = +
 
        4'b0000: so9 <= 0;                       // + + + = +
 
        4'b0001: so9 <= !a_gt_b8;       // + + - = sign of larger
 
        4'b0001: so9 <= !a_gt_b8;       // + + - = sign of larger
 
        4'b0010: so9 <= !a_gt_b8;       // + - + = sign of larger
 
        4'b0010: so9 <= !a_gt_b8;       // + - + = sign of larger
 
        4'b0011: so9 <= 0;                       // + - - = +
 
        4'b0011: so9 <= 0;                       // + - - = +
Line 561... Line 547... 
        endcase
 
        endcase
 
 
 
 
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
// Clock #10
 
// Clock #10
 
// Compute the difference in exponents, provides shift amount
 
// Compute the difference in exponents, provides shift amount
 
 
 
// Note that ex9a will be negative for an underflow condition
 
 
 
// so it's added rather than subtracted from xc9 as -(-num)
 
 
 
// is the same as an add. The underflow is tracked rather than
 
 
 
// using extra bits in the exponent.
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
reg [EMSB:0] xdiff10;
 
reg [EMSB:0] xdiff10;
 
reg [FX:0] mfs;
 
reg [FX:0] mfs;
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) xdiff10 <= ex_gt_xc9 ? ex9a - xc9
 
        if (ce) xdiff10 <= ex_gt_xc9 ? ex9a - xc9
 
                                                                                                                                : (under9 ? xc9 + ex9a : xc9 - ex9a);
 
                                                                                                                                : (under9 ? xc9 + ex9a : xc9 - ex9a);
 
 
 
 
 
// determine which fraction to denormalize
 
// Determine which fraction to denormalize (the one with the
 
 
 
// smaller exponent is denormalized).
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) mfs <= ex_gt_xc9 ? {4'b0,fractc9,{FMSB+1{1'b0}}} : mo9;
 
        if (ce) mfs <= ex_gt_xc9 ? {4'b0,fractc9,{FMSB+1{1'b0}}} : mo9;
 
 
 
 
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
// Clock #11
 
// Clock #11
 
 
 
// Limit the size of the shifter to only bits needed.
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
reg [6:0] xdif11;
 
reg [7:0] xdif11;
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) xdif11 <= xdiff10 > FMSB+3 ? FMSB+3 : xdiff10;
 
        if (ce) xdif11 <= xdiff10 > FX+3 ? FX+3 : xdiff10;
 
 
 
 
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
// Clock #12
 
// Clock #12
 
// Determine the sticky bit
 
// Determine the sticky bit
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
 
 
 
 
wire sticky, sticky12;
 
wire sticky, sticky12;
 
wire [FX:0] mfs12;
 
wire [FX:0] mfs12;
 
wire [6:0] xdif12;
 
wire [7:0] xdif12;
 
 
 
 
 
generate
 
generate
 
begin
 
begin
 
if (WID==128)
 
if (WID==128)
 
    redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
 
    redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
Line 607... Line 599... 
end
 
end
 
endgenerate
 
endgenerate
 
 
 
 
 
// register inputs to shifter and shift
 
// register inputs to shifter and shift
 
delay1 #(1)    u122(.clk(clk), .ce(ce), .i(sticky), .o(sticky12) );
 
delay1 #(1)    u122(.clk(clk), .ce(ce), .i(sticky), .o(sticky12) );
 
delay1 #(7)    u123(.clk(clk), .ce(ce), .i(xdif11),   .o(xdif12) );
 
delay1 #(8)    u123(.clk(clk), .ce(ce), .i(xdif11),   .o(xdif12) );
 
delay2 #(FX+1) u124(.clk(clk), .ce(ce), .i(mfs), .o(mfs12) );
 
delay2 #(FX+1) u124(.clk(clk), .ce(ce), .i(mfs), .o(mfs12) );
 
 
 
 
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
// Clock #13
 
// Clock #13
 
// - denormalize operand
 
// - denormalize operand (shift right)
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
reg [FX+2:0] mfs13;
 
reg [FX+2:0] mfs13;
 
wire [FX:0] mo13;
 
wire [FX:0] mo13;
 
wire ex_gt_xc13;
 
wire ex_gt_xc13;
 
wire [FMSB+1:0] fractc13;
 
wire [FMSB+1:0] fractc13;
Line 624... Line 616... 
delay4 #(FX+1) u131 (.clk(clk), .ce(ce), .i(mo9), .o(mo13));
 
delay4 #(FX+1) u131 (.clk(clk), .ce(ce), .i(mo9), .o(mo13));
 
delay4 u132 (.clk(clk), .ce(ce), .i(ex_gt_xc9), .o(ex_gt_xc13));
 
delay4 u132 (.clk(clk), .ce(ce), .i(ex_gt_xc9), .o(ex_gt_xc13));
 
vtdl #(FMSB+2) u133 (.clk(clk), .ce(ce), .a(4'd3), .d(fractc9), .q(fractc13));
 
vtdl #(FMSB+2) u133 (.clk(clk), .ce(ce), .a(4'd3), .d(fractc9), .q(fractc13));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) mfs13 <= ({mfs12,2'b0} >> xdif12)|{sticky12,1'b0};
 
        if (ce) mfs13 <= ({mfs12,2'b0} >> xdif12)|sticky12;
 
 
 
 
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
// Clock #14
 
// Clock #14
 
// Sort operands
 
// Sort operands
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
reg [FX+2:0] oa, ob;
 
reg [FX+2:0] oa, ob;
 
wire a_gt_b14;
 
wire a_gt_b14;
 
 
 
 
 
vtdl u141 (.clk(clk), .ce(ce), .a(4'd5), .d(a_gt_b8), .q(a_gt_b14));
 
vtdl #(1) u141 (.clk(clk), .ce(ce), .a(4'd5), .d(a_gt_b8), .q(a_gt_b14));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) oa <= ex_gt_xc13 ? {mo13,2'b00} : mfs13;
 
        if (ce) oa <= ex_gt_xc13 ? {mo13,2'b00} : mfs13;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) ob <= ex_gt_xc13 ? mfs13 : {fractc13,{FMSB+1{1'b0}},2'b00};
 
        if (ce) ob <= ex_gt_xc13 ? mfs13 : {fractc13,{FMSB+1{1'b0}},2'b00};
Line 648... Line 640... 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
reg [FX+2:0] oaa, obb;
 
reg [FX+2:0] oaa, obb;
 
wire realOp15;
 
wire realOp15;
 
wire [EMSB:0] ex15;
 
wire [EMSB:0] ex15;
 
 
 
 
 
vtdl u151 (.clk(clk), .ce(ce), .a(4'd7), .d(realOp7), .q(realOp15));
 
vtdl #(1) u151 (.clk(clk), .ce(ce), .a(4'd7), .d(realOp7), .q(realOp15));
 
vtdl #(EMSB+1) u152 (.clk(clk), .ce(ce), .a(4'd5), .d(ex9), .q(ex15));
 
vtdl #(EMSB+1) u152 (.clk(clk), .ce(ce), .a(4'd5), .d(ex9), .q(ex15));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) oaa <= a_gt_b14 ? oa : ob;
 
        if (ce) oaa <= a_gt_b14 ? oa : ob;
 
always @(posedge clk)
 
always @(posedge clk)
Line 670... Line 662... 
wire cNan16;
 
wire cNan16;
 
wire aInf16, cInf16;
 
wire aInf16, cInf16;
 
wire op16;
 
wire op16;
 
wire exinf16;
 
wire exinf16;
 
 
 
 
 
vtdl u161 (.clk(clk), .ce(ce), .a(4'd10), .d(qNaNOut5|aNan5|bNan5), .q(Nan16));
 
vtdl #(1) u161 (.clk(clk), .ce(ce), .a(4'd10), .d(qNaNOut5|aNan5|bNan5), .q(Nan16));
 
vtdl u162 (.clk(clk), .ce(ce), .a(4'd14), .d(cNan1), .q(cNan16));
 
vtdl #(1) u162 (.clk(clk), .ce(ce), .a(4'd14), .d(cNan1), .q(cNan16));
 
vtdl u163 (.clk(clk), .ce(ce), .a(4'd9), .d(exinf6), .q(aInf16));
 
vtdl #(1) u163 (.clk(clk), .ce(ce), .a(4'd9), .d(exinf6), .q(aInf16));
 
vtdl u164 (.clk(clk), .ce(ce), .a(4'd14), .d(cInf1), .q(cInf16));
 
vtdl #(1) u164 (.clk(clk), .ce(ce), .a(4'd14), .d(cInf1), .q(cInf16));
 
vtdl u165 (.clk(clk), .ce(ce), .a(4'd14), .d(op1), .q(op16));
 
vtdl #(1) u165 (.clk(clk), .ce(ce), .a(4'd14), .d(op1), .q(op16));
 
delay3 #(FX+1) u166 (.clk(clk), .ce(ce), .i(mo13), .o(mo16));
 
delay3 #(FX+1) u166 (.clk(clk), .ce(ce), .i(mo13), .o(mo16));
 
vtdl #(FMSB+2) u167 (.clk(clk), .ce(ce), .a(4'd6), .d(fractc9), .q(fractc16));
 
vtdl #(FMSB+2) u167 (.clk(clk), .ce(ce), .a(4'd6), .d(fractc9), .q(fractc16));
 
delay1 u169 (.clk(clk), .ce(ce), .i(&ex15), .o(exinf16));
 
delay1 u169 (.clk(clk), .ce(ce), .i(&ex15), .o(exinf16));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) mab = realOp15 ? oaa - obb : oaa + obb;
 
        if (ce) mab <= realOp15 ? oaa - obb : oaa + obb;
 
 
 
 
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
// Clock #17
 
// Clock #17
 
// - adjust for Nans
 
// - adjust for Nans
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
wire [EMSB:0] ex17;
 
wire [EMSB:0] ex17;
 
reg [FX:0] mo17;
 
reg [FX:0] mo17;
 
wire so17;
 
wire so17;
 
 
 
 
 
vtdl             u171 (.clk(clk), .ce(ce), .a(4'd7), .d(so9), .q(so17));
 
vtdl #(1)        u171 (.clk(clk), .ce(ce), .a(4'd7), .d(so9), .q(so17));
 
delay2 #(EMSB+1) u172 (.clk(clk), .ce(ce), .i(ex15), .o(ex17));
 
delay2 #(EMSB+1) u172 (.clk(clk), .ce(ce), .i(ex15), .o(ex17));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        casez({aInf16&cInf16,Nan16,cNan16,exinf16})
 
        casez({aInf16&cInf16,Nan16,cNan16,exinf16})
 
        4'b1???:        mo17 <= {1'b0,op16,{FMSB-1{1'b0}},op16,{FMSB{1'b0}}};   // inf +/- inf - generate QNaN on subtract, inf on add
 
        4'b1???:        mo17 <= {1'b0,op16,{FMSB-1{1'b0}},op16,{FMSB{1'b0}}};   // inf +/- inf - generate QNaN on subtract, inf on add
Line 704... Line 696... 
        default:        mo17 <= mab[FX+3:2];            // mab has an extra lead bit and two trailing bits
 
        default:        mo17 <= mab[FX+3:2];            // mab has an extra lead bit and two trailing bits
 
        endcase
 
        endcase
 
 
 
 
 
assign o = {so17,ex17,mo17};
 
assign o = {so17,ex17,mo17};
 
 
 
 
 
vtdl u173 (.clk(clk), .ce(ce), .a(4'd11), .d(over5),  .q(overflow) );
 
// The following are from the multiplier!!!
 
vtdl u174 (.clk(clk), .ce(ce), .a(4'd11), .d(over5),  .q(inf) );
 
vtdl #(1) u173 (.clk(clk), .ce(ce), .a(4'd11), .d(over5),  .q(overflow) );
 
vtdl u175 (.clk(clk), .ce(ce), .a(4'd11), .d(under5), .q(underflow) );
 
vtdl #(1) u174 (.clk(clk), .ce(ce), .a(4'd11), .d(over5),  .q(inf) );
 
 
 
vtdl #(1) u175 (.clk(clk), .ce(ce), .a(4'd11), .d(under5), .q(underflow) );
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
// Multiplier with normalization and rounding.
 
// Multiplier with normalization and rounding.

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