| Line 44... |
Line 44... |
//
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//
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// ============================================================================
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// ============================================================================
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module fpFMA (clk, ce, op, rm, a, b, c, o, inf);
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module fpFMA (clk, ce, op, rm, a, b, c, o, inf);
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parameter WID = 32;
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parameter WID = 32;
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localparam MSB = WID-1;
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`include "fpSize.sv"
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input clk;
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input clk;
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input ce;
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input ce;
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input op; // operation 0 = add, 1 = subtract
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input op; // operation 0 = add, 1 = subtract
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input [2:0] rm;
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input [2:0] rm;
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| Line 152... |
Line 127... |
if (ce) realOp2 <= op1 ^ (sa1 ^ sb1) ^ sc1;
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if (ce) realOp2 <= op1 ^ (sa1 ^ sb1) ^ sc1;
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reg [FX:0] fract5;
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reg [FX:0] fract5;
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generate
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generate
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if (WID==80) begin
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if (WID==84) begin
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reg [33:0] p00,p01,p02,p03;
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reg [33:0] p10,p11,p12,p13;
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reg [33:0] p20,p21,p22,p23;
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reg [33:0] p30,p31,p32,p33;
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reg [135:0] fract3a;
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reg [135:0] fract3b;
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reg [135:0] fract3c;
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reg [135:0] fract3d;
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reg [135:0] fract4a;
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reg [135:0] fract4b;
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always @(posedge clk)
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if (ce) begin
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p00 <= fracta1[16: 0] * fractb1[16: 0];
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p01 <= fracta1[33:17] * fractb1[16: 0];
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p02 <= fracta1[50:34] * fractb1[16: 0];
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p03 <= fracta1[67:51] * fractb1[16: 0];
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p10 <= fracta1[16: 0] * fractb1[33:17];
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p11 <= fracta1[33:17] * fractb1[33:17];
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p12 <= fracta1[50:34] * fractb1[33:17];
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p13 <= fracta1[67:51] * fractb1[33:17];
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p20 <= fracta1[16: 0] * fractb1[50:34];
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p21 <= fracta1[33:17] * fractb1[50:34];
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p22 <= fracta1[50:34] * fractb1[50:34];
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p23 <= fracta1[67:51] * fractb1[50:34];
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p30 <= fracta1[15: 0] * fractb1[67:51];
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p31 <= fracta1[31:16] * fractb1[67:51];
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p32 <= fracta1[47:32] * fractb1[67:51];
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p33 <= fracta1[63:48] * fractb1[67:51];
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end
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always @(posedge clk)
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if (ce) begin
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fract3a <= {p33,p31,p20,p00};
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fract3b <= {p32,p12,p10,17'b0} + {p23,p03,p01,17'b0};
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fract3c <= {p22,p11,34'b0} + {p13,p02,34'b0};
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fract3d <= {p12,51'b0} + {p03,51'b0};
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end
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always @(posedge clk)
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if (ce) begin
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fract4a <= fract3a + fract3b;
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fract4b <= fract3c + fract3d;
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end
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always @(posedge clk)
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if (ce) begin
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fract5 <= fract4a + fract4b;
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end
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end
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else if (WID==80) begin
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reg [31:0] p00,p01,p02,p03;
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reg [31:0] p00,p01,p02,p03;
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reg [31:0] p10,p11,p12,p13;
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reg [31:0] p10,p11,p12,p13;
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reg [31:0] p20,p21,p22,p23;
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reg [31:0] p20,p21,p22,p23;
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reg [31:0] p30,p31,p32,p33;
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reg [31:0] p30,p31,p32,p33;
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reg [127:0] fract3a;
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reg [127:0] fract3a;
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| Line 504... |
Line 530... |
reg so9;
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reg so9;
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reg [EMSB:0] ex9;
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reg [EMSB:0] ex9;
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reg [EMSB:0] ex9a;
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reg [EMSB:0] ex9a;
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reg ex_gt_xc9;
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reg ex_gt_xc9;
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reg [EMSB:0] xc9;
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reg [EMSB:0] xc9;
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reg a_gt_c9;
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wire [FX:0] mo9;
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wire [FX:0] mo9;
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wire [FMSB+1:0] fractc9;
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wire [FMSB+1:0] fractc9;
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wire under9;
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wire under9;
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wire xeq9;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) ex_gt_xc9 <= ex_gt_xc8;
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if (ce) ex_gt_xc9 <= ex_gt_xc8;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) a_gt_c9 <= a_gt_b8;
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always @(posedge clk)
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if (ce) xc9 <= xc8;
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if (ce) xc9 <= xc8;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) ex9a <= ex8;
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if (ce) ex9a <= ex8;
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delay3 #(FX+1) u93 (.clk(clk), .ce(ce), .i(mo6), .o(mo9));
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delay3 #(FX+1) u93 (.clk(clk), .ce(ce), .i(mo6), .o(mo9));
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delay3 #(FMSB+2) u94 (.clk(clk), .ce(ce), .i(fractc6), .o(fractc9));
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delay3 #(FMSB+2) u94 (.clk(clk), .ce(ce), .i(fractc6), .o(fractc9));
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delay3 u95 (.clk(clk), .ce(ce), .i(under6), .o(under9));
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delay3 u95 (.clk(clk), .ce(ce), .i(under6), .o(under9));
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delay2 u96 (.clk(clk), .ce(ce), .i(xeq7), .o(xeq9));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) ex9 <= resZero8 ? 0 : ex_gt_xc8 ? ex8 : xc8;
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if (ce) ex9 <= resZero8 ? 0 : ex_gt_xc8 ? ex8 : xc8;
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// Compute output sign
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// Compute output sign
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| Line 554... |
Line 585... |
// is the same as an add. The underflow is tracked rather than
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// is the same as an add. The underflow is tracked rather than
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// using extra bits in the exponent.
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// using extra bits in the exponent.
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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reg [EMSB:0] xdiff10;
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reg [EMSB:0] xdiff10;
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reg [FX:0] mfs;
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reg [FX:0] mfs;
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reg ops10;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xdiff10 <= ex_gt_xc9 ? ex9a - xc9
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if (ce) xdiff10 <= ex_gt_xc9 ? ex9a - xc9
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: (under9 ? xc9 + ex9a : xc9 - ex9a);
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: (under9 ? xc9 + ex9a : xc9 - ex9a);
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// Determine which fraction to denormalize (the one with the
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// Determine which fraction to denormalize (the one with the
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// smaller exponent is denormalized).
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// smaller exponent is denormalized). If the exponents are equal
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// denormalize the smaller fraction.
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always @(posedge clk)
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if (ce) mfs <=
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xeq9 ? (a_gt_c9 ? {4'b0,fractc9,{FMSB+1{1'b0}}} : mo9)
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: ex_gt_xc9 ? {4'b0,fractc9,{FMSB+1{1'b0}}} : mo9;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) mfs <= ex_gt_xc9 ? {4'b0,fractc9,{FMSB+1{1'b0}}} : mo9;
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if (ce) ops10 <= xeq9 ? (a_gt_c9 ? 1'b1 : 1'b0)
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: (ex_gt_xc9 ? 1'b1 : 1'b0);
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// Clock #11
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// Clock #11
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// Limit the size of the shifter to only bits needed.
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// Limit the size of the shifter to only bits needed.
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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| Line 588... |
Line 627... |
begin
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begin
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if (WID==128)
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if (WID==128)
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redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==96)
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else if (WID==96)
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redor96 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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redor96 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==84)
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redor84 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==80)
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else if (WID==80)
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redor80 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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redor80 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==64)
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else if (WID==64)
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redor64 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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redor64 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==32)
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else if (WID==32)
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| Line 610... |
Line 651... |
// -----------------------------------------------------------
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// -----------------------------------------------------------
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reg [FX+2:0] mfs13;
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reg [FX+2:0] mfs13;
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wire [FX:0] mo13;
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wire [FX:0] mo13;
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wire ex_gt_xc13;
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wire ex_gt_xc13;
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wire [FMSB+1:0] fractc13;
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wire [FMSB+1:0] fractc13;
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wire ops13;
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delay4 #(FX+1) u131 (.clk(clk), .ce(ce), .i(mo9), .o(mo13));
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delay4 #(FX+1) u131 (.clk(clk), .ce(ce), .i(mo9), .o(mo13));
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delay4 u132 (.clk(clk), .ce(ce), .i(ex_gt_xc9), .o(ex_gt_xc13));
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delay4 u132 (.clk(clk), .ce(ce), .i(ex_gt_xc9), .o(ex_gt_xc13));
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vtdl #(FMSB+2) u133 (.clk(clk), .ce(ce), .a(4'd3), .d(fractc9), .q(fractc13));
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vtdl #(FMSB+2) u133 (.clk(clk), .ce(ce), .a(4'd3), .d(fractc9), .q(fractc13));
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delay3 u134 (.clk(clk), .ce(ce), .i(ops10), .o(ops13));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) mfs13 <= ({mfs12,2'b0} >> xdif12)|sticky12;
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if (ce) mfs13 <= ({mfs12,2'b0} >> xdif12)|sticky12;
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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| Line 628... |
Line 671... |
wire a_gt_b14;
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wire a_gt_b14;
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vtdl #(1) u141 (.clk(clk), .ce(ce), .a(4'd5), .d(a_gt_b8), .q(a_gt_b14));
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vtdl #(1) u141 (.clk(clk), .ce(ce), .a(4'd5), .d(a_gt_b8), .q(a_gt_b14));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) oa <= ex_gt_xc13 ? {mo13,2'b00} : mfs13;
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if (ce) oa <= ops13 ? {mo13,2'b00} : mfs13;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) ob <= ex_gt_xc13 ? mfs13 : {fractc13,{FMSB+1{1'b0}},2'b00};
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if (ce) ob <= ops13 ? mfs13 : {fractc13,{FMSB+1{1'b0}},2'b00};
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// Clock #15
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// Clock #15
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// - Sort operands
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// - Sort operands
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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| Line 691... |
Line 734... |
casez({aInf16&cInf16,Nan16,cNan16,exinf16})
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casez({aInf16&cInf16,Nan16,cNan16,exinf16})
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4'b1???: mo17 <= {1'b0,op16,{FMSB-1{1'b0}},op16,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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4'b1???: mo17 <= {1'b0,op16,{FMSB-1{1'b0}},op16,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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4'b01??: mo17 <= {1'b0,mo16};
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4'b01??: mo17 <= {1'b0,mo16};
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4'b001?: mo17 <= {1'b0,fractc16[FMSB+1:0],{FMSB{1'b0}}};
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4'b001?: mo17 <= {1'b0,fractc16[FMSB+1:0],{FMSB{1'b0}}};
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4'b0001: mo17 <= 1'd0;
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4'b0001: mo17 <= 1'd0;
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default: mo17 <= mab[FX+3:2]; // mab has an extra lead bit and two trailing bits
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default: mo17 <= mab[FX+3:2]; // mab has two extra lead bits and two trailing bits
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endcase
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endcase
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assign o = {so17,ex17,mo17};
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assign o = {so17,ex17,mo17};
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// The following are from the multiplier!!!
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// The following are from the multiplier!!!
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| Line 708... |
Line 751... |
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// Multiplier with normalization and rounding.
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// Multiplier with normalization and rounding.
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module fpFMAnr(clk, ce, op, rm, a, b, c, o, sign_exe, inf, overflow, underflow);
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module fpFMAnr(clk, ce, op, rm, a, b, c, o, sign_exe, inf, overflow, underflow);
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parameter WID=32;
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parameter WID=32;
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localparam MSB = WID-1;
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`include "fpSize.sv"
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input clk;
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input clk;
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input ce;
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input ce;
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input op;
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input op;
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input [2:0] rm;
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input [2:0] rm;
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input [MSB:0] a, b, c;
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input [MSB:0] a, b, c;
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