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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpFMA.v] - Diff between revs 26 and 27

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Line 42... Line 42... 
//      +-inf * +-inf = -+inf   (this is handled by exOver)
 
//      +-inf * +-inf = -+inf   (this is handled by exOver)
 
//      +-inf * 0     = QNaN
 
//      +-inf * 0     = QNaN
 
//      
//      
// ============================================================================
 
// ============================================================================
 
 
 
 
 
module fpFMA (clk, ce, op, rm, a, b, c, o, inf);
 
module fpFMA (clk, ce, op, rm, a, b, c, o, under, over, inf, zero);
 
parameter WID = 32;
 
parameter WID = 32;
 
`include "fpSize.sv"
 
`include "fpSize.sv"
 
 
 
 
 
input clk;
 
input clk;
 
input ce;
 
input ce;
 
input op;               // operation 0 = add, 1 = subtract
 
input op;               // operation 0 = add, 1 = subtract
 
input [2:0] rm;
 
input [2:0] rm;
 
input  [WID:1] a, b, c;
 
input  [WID:1] a, b, c;
 
output [EX:0] o;
 
output [EX:0] o;
 
 
 
output under;
 
 
 
output over;
 
output inf;
 
output inf;
 
 
 
output zero;
 
 
 
 
 
// constants
 
// constants
 
wire [EMSB:0] infXp = {EMSB+1{1'b1}};    // infinite / NaN - all ones
 
wire [EMSB:0] infXp = {EMSB+1{1'b1}};    // infinite / NaN - all ones
 
// The following is the value for an exponent of zero, with the offset
 
// The following is the value for an exponent of zero, with the offset
 
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
 
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
Line 76... Line 79... 
wire a_dn1, b_dn1, c_dn1;                       // a/b is denormalized
 
wire a_dn1, b_dn1, c_dn1;                       // a/b is denormalized
 
wire aNan1, bNan1, cNan1;
 
wire aNan1, bNan1, cNan1;
 
wire az1, bz1, cz1;
 
wire az1, bz1, cz1;
 
wire aInf1, bInf1, cInf1;
 
wire aInf1, bInf1, cInf1;
 
reg op1;
 
reg op1;
 
wire xcInf1;
 
 
 
 
 
 
 
fpDecompReg #(WID) u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa1), .exp(xa1), .fract(fracta1), .xz(a_dn1), .vz(az1), .inf(aInf1), .nan(aNan1) );
 
fpDecompReg #(WID) u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa1), .exp(xa1), .fract(fracta1), .xz(a_dn1), .vz(az1), .inf(aInf1), .nan(aNan1) );
 
fpDecompReg #(WID) u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb1), .exp(xb1), .fract(fractb1), .xz(b_dn1), .vz(bz1), .inf(bInf1), .nan(bNan1) );
 
fpDecompReg #(WID) u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb1), .exp(xb1), .fract(fractb1), .xz(b_dn1), .vz(bz1), .inf(bInf1), .nan(bNan1) );
 
fpDecompReg #(WID) u1c (.clk(clk), .ce(ce), .i(c), .sgn(sc1), .exp(xc1), .fract(fractc1), .xz(c_dn1), .vz(cz1), .inf(cInf1), .nan(cNan1) );
 
fpDecompReg #(WID) u1c (.clk(clk), .ce(ce), .i(c), .sgn(sc1), .exp(xc1), .fract(fractc1), .xz(c_dn1), .vz(cz1), .inf(cInf1), .nan(cNan1) );
 
 
 
 
Line 387... Line 389... 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
 
 
 
 
// Status
 
// Status
 
reg under5;
 
reg under5;
 
reg over5;
 
reg over5;
 
reg [EMSB:0] ex5;
 
reg [EMSB+2:0] ex5;
 
reg [EMSB:0] xc5;
 
reg [EMSB:0] xc5;
 
wire aInf5, bInf5;
 
wire aInf5, bInf5;
 
wire aNan5, bNan5;
 
wire aNan5, bNan5;
 
wire qNaNOut5;
 
wire qNaNOut5;
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) under5 <= ex4[EMSB+2];
 
        if (ce) under5 <= ex4[EMSB+2];
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) over5 <= (&ex4[EMSB:0] | ex4[EMSB+1]) & !ex4[EMSB+2];
 
        if (ce) over5 <= (&ex4[EMSB:0] | ex4[EMSB+1]) & !ex4[EMSB+2];
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) ex5 <= ex4[EMSB:0];
 
        if (ce) ex5 <= ex4;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) xc5 <= xc4;
 
        if (ce) xc5 <= xc4;
 
 
 
 
 
delay4 u2a (.clk(clk), .ce(ce), .i(aInf1), .o(aInf5) );
 
delay4 u2a (.clk(clk), .ce(ce), .i(aInf1), .o(aInf5) );
 
delay4 u2b (.clk(clk), .ce(ce), .i(bInf1), .o(bInf5) );
 
delay4 u2b (.clk(clk), .ce(ce), .i(bInf1), .o(bInf5) );
Line 421... Line 423... 
// - figure multiplier exponent output
 
// - figure multiplier exponent output
 
// - correct xponent and mantissa for exceptional conditions
 
// - correct xponent and mantissa for exceptional conditions
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
 
 
 
 
reg [FX:0] mo6;
 
reg [FX:0] mo6;
 
reg [EMSB:0] ex6;
 
reg [EMSB+2:0] ex6;
 
reg [EMSB:0] xc6;
 
reg [EMSB:0] xc6;
 
reg exinf6;
 
 
 
wire [FMSB+1:0] fractc6;
 
wire [FMSB+1:0] fractc6;
 
delay5 #(FMSB+2) u61 (.clk(clk), .ce(ce), .i(fractc1), .o(fractc6) );
 
delay5 #(FMSB+2) u61 (.clk(clk), .ce(ce), .i(fractc1), .o(fractc6) );
 
delay1 u62 (.clk(clk), .ce(ce), .i(under5), .o(under6));
 
delay1 u62 (.clk(clk), .ce(ce), .i(under5), .o(under6));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
Line 450... Line 451... 
                casez({qNaNOut5|aNan5|bNan5,aInf5,bInf5,over5,under5})
 
                casez({qNaNOut5|aNan5|bNan5,aInf5,bInf5,over5,under5})
 
                5'b1????:       ex6 <= infXp;   // qNaN - infinity * zero
 
                5'b1????:       ex6 <= infXp;   // qNaN - infinity * zero
 
                5'b01???:       ex6 <= infXp;   // 'a' infinite
 
                5'b01???:       ex6 <= infXp;   // 'a' infinite
 
                5'b001??:       ex6 <= infXp;   // 'b' infinite
 
                5'b001??:       ex6 <= infXp;   // 'b' infinite
 
                5'b0001?:       ex6 <= infXp;   // result overflow
 
                5'b0001?:       ex6 <= infXp;   // result overflow
 
                5'b00001:       ex6 <= ex5[EMSB:0];//0;          // underflow
 
                5'b00001:       ex6 <= ex5;             //0;            // underflow
 
                default:        ex6 <= ex5[EMSB:0];      // situation normal
 
                default:        ex6 <= ex5;             // situation normal
 
                endcase
 
                endcase
 
 
 
 
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
// Clock #7
 
// Clock #7
 
// - prep for addition, determine greater operand
 
// - prep for addition, determine greater operand
Line 467... Line 468... 
wire az7, bz7, cz7;
 
wire az7, bz7, cz7;
 
wire realOp7;
 
wire realOp7;
 
 
 
 
 
// which has greater magnitude ? Used for sign calc
 
// which has greater magnitude ? Used for sign calc
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) ex_gt_xc7 <= (ex6 > xc6) && !under6;
 
        if (ce) ex_gt_xc7 <= $signed(ex6) > $signed({2'b0,xc6});
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) xeq7 <= (ex6==xc6) && !under6;
 
        if (ce) xeq7 <= (ex6=={2'b0,xc6});
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) ma_gt_mc7 <= mo6 > {fractc6,{FMSB+1{1'b0}}};
 
        if (ce) ma_gt_mc7 <= mo6 > {fractc6,{FMSB+1{1'b0}}};
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) meq7 <= mo6 == {fractc6,{FMSB+1{1'b0}}};
 
        if (ce) meq7 <= mo6 == {fractc6,{FMSB+1{1'b0}}};
 
vtdl #(1) u71 (.clk(clk), .ce(ce), .a(4'd5), .d(az1), .q(az7));
 
vtdl #(1) u71 (.clk(clk), .ce(ce), .a(4'd5), .d(az1), .q(az7));
Line 488... Line 489... 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
 
 
 
 
reg a_gt_b8;
 
reg a_gt_b8;
 
reg resZero8;
 
reg resZero8;
 
reg ex_gt_xc8;
 
reg ex_gt_xc8;
 
wire [EMSB:0] ex8;
 
wire [EMSB+2:0] ex8;
 
wire [EMSB:0] xc8;
 
wire [EMSB:0] xc8;
 
wire xcInf8;
 
wire xcInf8;
 
wire [2:0] rm8;
 
wire [2:0] rm8;
 
wire op8;
 
wire op8;
 
wire sa8, sb8, sc8;
 
wire sa8, sc8;
 
 
 
 
 
delay2 #(EMSB+1) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8));
 
delay2 #(EMSB+3) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8));
 
delay2 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xc6), .o(xc8));
 
delay2 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xc6), .o(xc8));
 
vtdl #(1) u83 (.clk(clk), .ce(ce), .a(4'd5), .d(xcInf2), .q(xcInf8));
 
vtdl #(1) u83 (.clk(clk), .ce(ce), .a(4'd5), .d(xcInf2), .q(xcInf8));
 
vtdl #(3) u84 (.clk(clk), .ce(ce), .a(4'd7), .d(rm), .q(rm8));
 
vtdl #(3) u84 (.clk(clk), .ce(ce), .a(4'd7), .d(rm), .q(rm8));
 
vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd6), .d(op1), .q(op8));
 
vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd6), .d(op1), .q(op8));
 
vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd7), .d(sa1 ^ sb1), .q(sa8));
 
vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd6), .d(sa1 ^ sb1), .q(sa8));
 
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd7), .d(sc1), .q(sc8));
 
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd6), .d(sc1), .q(sc8));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) ex_gt_xc8 <= ex_gt_xc7;
 
        if (ce) ex_gt_xc8 <= ex_gt_xc7;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce)
 
        if (ce)
Line 526... Line 527... 
// numbers are equal, in which case the exponent should be
 
// numbers are equal, in which case the exponent should be
 
// zero.
 
// zero.
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
 
 
 
 
reg so9;
 
reg so9;
 
reg [EMSB:0] ex9;
 
reg [EMSB+2:0] ex9;
 
reg [EMSB:0] ex9a;
 
reg [EMSB+2:0] ex9a;
 
reg ex_gt_xc9;
 
reg ex_gt_xc9;
 
reg [EMSB:0] xc9;
 
reg [EMSB:0] xc9;
 
reg a_gt_c9;
 
reg a_gt_c9;
 
wire [FX:0] mo9;
 
wire [FX:0] mo9;
 
wire [FMSB+1:0] fractc9;
 
wire [FMSB+1:0] fractc9;
Line 551... Line 552... 
delay3 #(FMSB+2) u94 (.clk(clk), .ce(ce), .i(fractc6), .o(fractc9));
 
delay3 #(FMSB+2) u94 (.clk(clk), .ce(ce), .i(fractc6), .o(fractc9));
 
delay3 u95 (.clk(clk), .ce(ce), .i(under6), .o(under9));
 
delay3 u95 (.clk(clk), .ce(ce), .i(under6), .o(under9));
 
delay2 u96 (.clk(clk), .ce(ce), .i(xeq7), .o(xeq9));
 
delay2 u96 (.clk(clk), .ce(ce), .i(xeq7), .o(xeq9));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) ex9 <= resZero8 ? 0 : ex_gt_xc8 ? ex8 : xc8;
 
        if (ce) ex9 <= resZero8 ? 1'd0 : ex_gt_xc8 ? ex8 : {2'b0,xc8};
 
 
 
 
 
// Compute output sign
 
// Compute output sign
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce)
 
        if (ce)
 
        case ({resZero8,sa8,op8,sc8})   // synopsys full_case parallel_case
 
        case ({resZero8,sa8,op8,sc8})   // synopsys full_case parallel_case
Line 583... Line 584... 
// Note that ex9a will be negative for an underflow condition
 
// Note that ex9a will be negative for an underflow condition
 
// so it's added rather than subtracted from xc9 as -(-num)
 
// so it's added rather than subtracted from xc9 as -(-num)
 
// is the same as an add. The underflow is tracked rather than
 
// is the same as an add. The underflow is tracked rather than
 
// using extra bits in the exponent.
 
// using extra bits in the exponent.
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
reg [EMSB:0] xdiff10;
 
reg [EMSB+2:0] xdiff10;
 
reg [FX:0] mfs;
 
reg [FX:0] mfs;
 
reg ops10;
 
reg ops10;
 
 
 
 
 
 
 
// If the multiplier exponent was negative (underflowed) then
 
 
 
// the mantissa needs to be shifted right even more (until
 
 
 
// the exponent is zero. The total shift would be xc9-0-
 
 
 
// amount underflows which is xc9 + -ex9a.
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) xdiff10 <= ex_gt_xc9 ? ex9a - xc9
 
        if (ce) xdiff10 <= ex_gt_xc9 ? ex9a - xc9
 
                                                                                                                                : (under9 ? xc9 + ex9a : xc9 - ex9a);
 
                                                                                : ex9a[EMSB+2] ? xc9 + (~ex9a+2'd1)
 
 
 
                                                                                : xc9 - ex9a;
 
 
 
 
 
// Determine which fraction to denormalize (the one with the
 
// Determine which fraction to denormalize (the one with the
 
// smaller exponent is denormalized). If the exponents are equal
 
// smaller exponent is denormalized). If the exponents are equal
 
// denormalize the smaller fraction.
 
// denormalize the smaller fraction.
 
always @(posedge clk)
 
always @(posedge clk)
Line 682... Line 689... 
// - Sort operands
 
// - Sort operands
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
reg [FX+2:0] oaa, obb;
 
reg [FX+2:0] oaa, obb;
 
wire realOp15;
 
wire realOp15;
 
wire [EMSB:0] ex15;
 
wire [EMSB:0] ex15;
 
 
 
wire [EMSB:0] ex9c = ex9[EMSB+1] ? infXp : ex9[EMSB:0];
 
 
 
wire overflow15;
 
vtdl #(1) u151 (.clk(clk), .ce(ce), .a(4'd7), .d(realOp7), .q(realOp15));
 
vtdl #(1) u151 (.clk(clk), .ce(ce), .a(4'd7), .d(realOp7), .q(realOp15));
 
vtdl #(EMSB+1) u152 (.clk(clk), .ce(ce), .a(4'd5), .d(ex9), .q(ex15));
 
vtdl #(EMSB+1) u152 (.clk(clk), .ce(ce), .a(4'd5), .d(ex9c), .q(ex15));
 
 
 
vtdl #(EMSB+1) u153 (.clk(clk), .ce(ce), .a(4'd5), .d(ex9[EMSB+1]| &ex9[EMSB:0]), .q(overflow15));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) oaa <= a_gt_b14 ? oa : ob;
 
        if (ce) oaa <= a_gt_b14 ? oa : ob;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) obb <= a_gt_b14 ? ob : oa;
 
        if (ce) obb <= a_gt_b14 ? ob : oa;
Line 707... Line 716... 
wire op16;
 
wire op16;
 
wire exinf16;
 
wire exinf16;
 
 
 
 
 
vtdl #(1) u161 (.clk(clk), .ce(ce), .a(4'd10), .d(qNaNOut5|aNan5|bNan5), .q(Nan16));
 
vtdl #(1) u161 (.clk(clk), .ce(ce), .a(4'd10), .d(qNaNOut5|aNan5|bNan5), .q(Nan16));
 
vtdl #(1) u162 (.clk(clk), .ce(ce), .a(4'd14), .d(cNan1), .q(cNan16));
 
vtdl #(1) u162 (.clk(clk), .ce(ce), .a(4'd14), .d(cNan1), .q(cNan16));
 
vtdl #(1) u163 (.clk(clk), .ce(ce), .a(4'd9), .d(exinf6), .q(aInf16));
 
vtdl #(1) u163 (.clk(clk), .ce(ce), .a(4'd9), .d(&ex6), .q(aInf16));
 
vtdl #(1) u164 (.clk(clk), .ce(ce), .a(4'd14), .d(cInf1), .q(cInf16));
 
vtdl #(1) u164 (.clk(clk), .ce(ce), .a(4'd14), .d(cInf1), .q(cInf16));
 
vtdl #(1) u165 (.clk(clk), .ce(ce), .a(4'd14), .d(op1), .q(op16));
 
vtdl #(1) u165 (.clk(clk), .ce(ce), .a(4'd14), .d(op1), .q(op16));
 
delay3 #(FX+1) u166 (.clk(clk), .ce(ce), .i(mo13), .o(mo16));
 
delay3 #(FX+1) u166 (.clk(clk), .ce(ce), .i(mo13), .o(mo16));
 
vtdl #(FMSB+2) u167 (.clk(clk), .ce(ce), .a(4'd6), .d(fractc9), .q(fractc16));
 
vtdl #(FMSB+2) u167 (.clk(clk), .ce(ce), .a(4'd6), .d(fractc9), .q(fractc16));
 
delay1 u169 (.clk(clk), .ce(ce), .i(&ex15), .o(exinf16));
 
delay1 u169 (.clk(clk), .ce(ce), .i(&ex15), .o(exinf16));
Line 724... Line 733... 
// - adjust for Nans
 
// - adjust for Nans
 
// -----------------------------------------------------------
 
// -----------------------------------------------------------
 
wire [EMSB:0] ex17;
 
wire [EMSB:0] ex17;
 
reg [FX:0] mo17;
 
reg [FX:0] mo17;
 
wire so17;
 
wire so17;
 
 
 
wire exinf17;
 
 
 
wire overflow17;
 
 
 
 
 
vtdl #(1)        u171 (.clk(clk), .ce(ce), .a(4'd7), .d(so9), .q(so17));
 
vtdl #(1)        u171 (.clk(clk), .ce(ce), .a(4'd7), .d(so9), .q(so17));
 
delay2 #(EMSB+1) u172 (.clk(clk), .ce(ce), .i(ex15), .o(ex17));
 
delay2 #(EMSB+1) u172 (.clk(clk), .ce(ce), .i(ex15), .o(ex17));
 
 
 
delay1 #(1) u173 (.clk(clk), .ce(ce), .i(exinf16), .o(exinf17));
 
 
 
delay2 u174 (.clk(clk), .ce(ce), .i(overflow15), .o(overflow17));
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        casez({aInf16&cInf16,Nan16,cNan16,exinf16})
 
        casez({aInf16&cInf16,Nan16,cNan16,exinf16})
 
        4'b1???:        mo17 <= {1'b0,op16,{FMSB-1{1'b0}},op16,{FMSB{1'b0}}};   // inf +/- inf - generate QNaN on subtract, inf on add
 
        4'b1???:        mo17 <= {1'b0,op16,{FMSB-1{1'b0}},op16,{FMSB{1'b0}}};   // inf +/- inf - generate QNaN on subtract, inf on add
 
        4'b01??:        mo17 <= {1'b0,mo16};
 
        4'b01??:        mo17 <= {1'b0,mo16};
Line 738... Line 751... 
        4'b0001:        mo17 <= 1'd0;
 
        4'b0001:        mo17 <= 1'd0;
 
        default:        mo17 <= mab[FX+3:2];            // mab has two extra lead bits and two trailing bits
 
        default:        mo17 <= mab[FX+3:2];            // mab has two extra lead bits and two trailing bits
 
        endcase
 
        endcase
 
 
 
 
 
assign o = {so17,ex17,mo17};
 
assign o = {so17,ex17,mo17};
 
 
 
assign zero = {ex17,mo17}==1'd0;
 
// The following are from the multiplier!!!
 
assign inf = exinf17;
 
vtdl #(1) u173 (.clk(clk), .ce(ce), .a(4'd11), .d(over5),  .q(overflow) );
 
assign under = ex17==1'd0;
 
vtdl #(1) u174 (.clk(clk), .ce(ce), .a(4'd11), .d(over5),  .q(inf) );
 
assign over = overflow17;
 
vtdl #(1) u175 (.clk(clk), .ce(ce), .a(4'd11), .d(under5), .q(underflow) );
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
// Multiplier with normalization and rounding.
 
// Multiplier with normalization and rounding.
 
 
 
 
 
module fpFMAnr(clk, ce, op, rm, a, b, c, o, sign_exe, inf, overflow, underflow);
 
module fpFMAnr(clk, ce, op, rm, a, b, c, o, inf, overflow, underflow, inexact);
 
parameter WID=32;
 
parameter WID=64;
 
`include "fpSize.sv"
 
`include "fpSize.sv"
 
 
 
 
 
input clk;
 
input clk;
 
input ce;
 
input ce;
 
input op;
 
input op;
 
input [2:0] rm;
 
input [2:0] rm;
 
input  [MSB:0] a, b, c;
 
input  [MSB:0] a, b, c;
 
output [MSB:0] o;
 
output [MSB:0] o;
 
output sign_exe;
 
 
 
output inf;
 
output inf;
 
output overflow;
 
output overflow;
 
output underflow;
 
output underflow;
 
 
 
output inexact;
 
 
 
 
 
wire [EX:0] o1;
 
wire [EX:0] fma_o;
 
 
 
wire fma_underflow;
 
 
 
wire norm_underflow;
 
 
 
wire norm_inexact;
 
wire sign_exe1, inf1, overflow1, underflow1;
 
wire sign_exe1, inf1, overflow1, underflow1;
 
wire [MSB+3:0] fpn0;
 
wire [MSB+3:0] fpn0;
 
 
 
 
 
fpFMA       #(WID) u1 (clk, ce, op, rm, a, b, c, o1, inf1);
 
fpFMA #(WID) u1
 
fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) );
 
(
 
 
 
        .clk(clk),
 
 
 
        .ce(ce),
 
 
 
        .op(op),
 
 
 
        .rm(rm),
 
 
 
        .a(a),
 
 
 
        .b(b),
 
 
 
        .c(c),
 
 
 
        .o(fma_o),
 
 
 
        .under(fma_underflow),
 
 
 
        .inf()
 
 
 
);
 
 
 
fpNormalize #(WID) u2
 
 
 
(
 
 
 
        .clk(clk),
 
 
 
        .ce(ce),
 
 
 
        .i(fma_o),
 
 
 
        .o(fpn0),
 
 
 
        .under_i(fma_underflow),
 
 
 
        .under_o(norm_underflow),
 
 
 
        .inexact_o(norm_inexact)
 
 
 
);
 
fpRoundReg  #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
 
fpRoundReg  #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
 
delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
 
fpDecomp                #(WID) u4(.i(o), .xz(underflow), .inf(inf));
 
delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
 
delay1                  #(1)    u6 (.clk(clk), .ce(ce), .i(norm_inexact), .o(inexact));
 
 
 
assign overflow = inf;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
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