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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2016 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpMul.v
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// fpMul.v
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Line 55... |
localparam EMSB = WID==128 ? 14 :
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==52 ? 39 :
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WID==48 ? 35 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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WID==24 ? 15 : 9;
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// correct the exponent for denormalized operands
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// correct the exponent for denormalized operands
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// adjust the sum by the exponent offset (subtract 127)
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// adjust the sum by the exponent offset (subtract 127)
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// mul: ex1 = xa + xb, result should always be < 1ffh
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// mul: ex1 = xa + xb, result should always be < 1ffh
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assign ex1 = (az|bz) ? 0 : (xa|a_dn) + (xb|b_dn) - bias;
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assign ex1 = (az|bz) ? 0 : (xa|a_dn) + (xb|b_dn) - bias;
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generate
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if (WID==64) begin
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reg [35:0] p00,p01,p02;
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reg [35:0] p00,p01,p02;
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reg [35:0] p10,p11,p12;
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reg [35:0] p10,p11,p12;
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reg [35:0] p20,p21,p22;
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reg [35:0] p20,p21,p22;
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generate
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if (WID==64) begin
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always @(posedge clk)
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always @(posedge clk)
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if (ce) begin
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if (ce) begin
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p00 <= fracta[17: 0] * fractb[17: 0];
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p00 <= fracta[17: 0] * fractb[17: 0];
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p01 <= fracta[35:18] * fractb[17: 0];
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p01 <= fracta[35:18] * fractb[17: 0];
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p02 <= fracta[52:36] * fractb[17: 0];
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p02 <= fracta[52:36] * fractb[17: 0];
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Line 152... |
{p22,72'b0} + {p21,54'b0} + {p20,36'b0}
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{p22,72'b0} + {p21,54'b0} + {p20,36'b0}
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;
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;
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end
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end
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end
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end
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else if (WID==32) begin
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else if (WID==32) begin
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reg [23:0] p00,p01,p02;
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reg [23:0] p10,p11,p12;
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reg [23:0] p20,p21,p22;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) begin
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if (ce) begin
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p00 <= fracta[17: 0] * fractb[17: 0];
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p00 <= fracta[11: 0] * fractb[11: 0];
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p01 <= fracta[23:18] * fractb[17: 0];
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p01 <= fracta[23:12] * fractb[11: 0];
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p10 <= fracta[17: 0] * fractb[23:18];
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p10 <= fracta[11: 0] * fractb[23:12];
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p11 <= fracta[23:18] * fractb[23:18];
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p11 <= fracta[23:12] * fractb[23:12];
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fract1 <= {p11,p00} + {p01,18'b0} + {p10,18'b0};
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fract1 <= {p11,p00} + {p01,12'b0} + {p10,12'b0};
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end
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end
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end
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end
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else begin
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else begin
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reg [35:0] p00,p01,p02;
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reg [35:0] p10,p11,p12;
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reg [35:0] p20,p21,p22;
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce) begin
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fract1 <= fracta * fractb;
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fract1a <= fracta * fractb;
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fract1 <= fract1a;
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end
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end
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end
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endgenerate
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endgenerate
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// Status
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// Status
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wire under1, over1;
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wire under1, over1;
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wire under = ex1[EMSB+2]; // exponent underflow
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wire under = ex1[EMSB+2]; // exponent underflow
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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delay2 #(EMSB+1) u3 (.clk(clk), .ce(ce), .i(ex1[EMSB:0]), .o(ex2) );
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delay2 #(EMSB+1) u3 (.clk(clk), .ce(ce), .i(ex1[EMSB:0]), .o(ex2) );
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delay2 #(FX+1) u4 (.clk(clk), .ce(ce), .i(fract1), .o(fracto) );
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delay2 u2a (.clk(clk), .ce(ce), .i(aInf), .o(aInf1) );
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delay2 u2a (.clk(clk), .ce(ce), .i(aInf), .o(aInf1) );
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delay2 u2b (.clk(clk), .ce(ce), .i(bInf), .o(bInf1) );
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delay2 u2b (.clk(clk), .ce(ce), .i(bInf), .o(bInf1) );
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delay2 u6 (.clk(clk), .ce(ce), .i(under), .o(under1) );
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delay2 u6 (.clk(clk), .ce(ce), .i(under), .o(under1) );
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delay2 u7 (.clk(clk), .ce(ce), .i(over), .o(over1) );
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delay2 u7 (.clk(clk), .ce(ce), .i(over), .o(over1) );
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wire so1;
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wire so1;
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delay3 u8 (.clk(clk), .ce(ce), .i(sa ^ sb), .o(so1) );// two clock delay!
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delay3 u8 (.clk(clk), .ce(ce), .i(sa ^ sb), .o(so1) );// two clock delay!
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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casex({qNaNOut|aNan1|bNan1,aInf1,bInf1,over1,under1})
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casez({qNaNOut|aNan1|bNan1,aInf1,bInf1,over1,under1})
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5'b1xxxx: xo1 = infXp; // qNaN - infinity * zero
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5'b1????: xo1 = infXp; // qNaN - infinity * zero
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5'b01xxx: xo1 = infXp; // 'a' infinite
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5'b01???: xo1 = infXp; // 'a' infinite
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5'b001xx: xo1 = infXp; // 'b' infinite
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5'b001??: xo1 = infXp; // 'b' infinite
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5'b0001x: xo1 = infXp; // result overflow
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5'b0001?: xo1 = infXp; // result overflow
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5'b00001: xo1 = 0; // underflow
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5'b00001: xo1 = ex2[EMSB:0];//0; // underflow
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default: xo1 = ex2[EMSB:0]; // situation normal
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default: xo1 = ex2[EMSB:0]; // situation normal
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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casex({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1})
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casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1})
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6'b1xxxxx: mo1 = {1'b0,a1[FMSB:0],{FMSB+1{1'b0}}};
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6'b1?????: mo1 = {1'b0,a1[FMSB:0],{FMSB+1{1'b0}}};
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6'bx1xxxx: mo1 = {1'b0,b1[FMSB:0],{FMSB+1{1'b0}}};
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6'b01????: mo1 = {1'b0,b1[FMSB:0],{FMSB+1{1'b0}}};
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6'bxx1xxx: mo1 = {1'b0,qNaN|3'd4,{FMSB+1{1'b0}}}; // multiply inf * zero
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6'b001???: mo1 = {1'b0,qNaN|3'd4,{FMSB+1{1'b0}}}; // multiply inf * zero
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6'b0001xx: mo1 = 0; // mul inf's
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6'b0001??: mo1 = 0; // mul inf's
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6'b00001x: mo1 = 0; // mul inf's
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6'b00001?: mo1 = 0; // mul inf's
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6'b000001: mo1 = 0; // mul overflow
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6'b000001: mo1 = 0; // mul overflow
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default: mo1 = fracto;
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default: mo1 = fract1;
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endcase
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endcase
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delay3 u10 (.clk(clk), .ce(ce), .i(sa & sb), .o(sign_exe) );
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delay3 u10 (.clk(clk), .ce(ce), .i(sa & sb), .o(sign_exe) );
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delay1 u11 (.clk(clk), .ce(ce), .i(over1), .o(overflow) );
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delay1 u11 (.clk(clk), .ce(ce), .i(over1), .o(overflow) );
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delay1 u12 (.clk(clk), .ce(ce), .i(over1), .o(inf) );
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delay1 u12 (.clk(clk), .ce(ce), .i(over1), .o(inf) );
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Line 236... |
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assign o = {so1,xo1,mo1};
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assign o = {so1,xo1,mo1};
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endmodule
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endmodule
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module fpMulnr(clk, ce, a, b, o, rm, sign_exe, inf, overflow, underflow);
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parameter WID=32;
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localparam MSB = WID-1;
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input clk;
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input ce;
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input [MSB:0] a, b;
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output [MSB:0] o;
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input [2:0] rm;
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output sign_exe;
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output inf;
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output overflow;
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output underflow;
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wire [EX:0] o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire [MSB+3:0] fpn0;
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fpMul #(WID) u1 (clk, ce, a, b, o1, sign_exe1, inf1, overflow1, underflow1);
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fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(underflow1), .i(o1), .o(fpn0) );
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fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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endmodule
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module fpMul_tb();
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module fpMul_tb();
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reg clk;
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reg clk;
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initial begin
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initial begin
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clk = 0;
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clk = 0;
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