URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpMul.v] - Diff between revs 10 and 11

Rev 10	Rev 11
Line 218...	Line 218...
`endcase`	`endcase`

`always @(posedge clk)`	`always @(posedge clk)`
`if (ce)`	`if (ce)`
`casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1})`	`casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1})`
`6'b1?????: mo1 = {1'b0,a1[FMSB:0],{FMSB+1{1'b0}}};`	`6'b1?????: mo1 = {1'b1,a1[FMSB:0],{FMSB+1{1'b0}}};`
`6'b01????: mo1 = {1'b0,b1[FMSB:0],{FMSB+1{1'b0}}};`	`6'b01????: mo1 = {1'b1,b1[FMSB:0],{FMSB+1{1'b0}}};`
`6'b001???: mo1 = {1'b0,qNaN\|3'd4,{FMSB+1{1'b0}}}; // multiply inf * zero`	`6'b001???: mo1 = {1'b1,qNaN\|3'd4,{FMSB+1{1'b0}}}; // multiply inf * zero`
`6'b0001??: mo1 = 0; // mul inf's`	`6'b0001??: mo1 = 0; // mul inf's`
`6'b00001?: mo1 = 0; // mul inf's`	`6'b00001?: mo1 = 0; // mul inf's`
`6'b000001: mo1 = 0; // mul overflow`	`6'b000001: mo1 = 0; // mul overflow`
`default: mo1 = fract1;`	`default: mo1 = fract1;`
`endcase`	`endcase`