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Line 38... |
reg rst;
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reg rst;
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reg clk;
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reg clk;
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reg [12:0] adr;
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reg [12:0] adr;
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reg [95:0] mem [0:8191];
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reg [95:0] mem [0:8191];
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reg [95:0] memo [0:9000];
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reg [95:0] memo [0:9000];
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reg [31:0] a,b,a6,b6;
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reg [191:0] memd [0:8191];
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reg [191:0] memdo [0:9000];
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reg [31:0] a,b;
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wire [31:0] a5,b5;
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wire [31:0] a5,b5;
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wire [31:0] o;
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wire [31:0] o;
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reg [63:0] ad,bd;
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wire [63:0] ad5,bd5;
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wire [63:0] od;
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initial begin
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initial begin
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rst = 1'b0;
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rst = 1'b0;
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clk = 1'b0;
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clk = 1'b0;
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adr = 0;
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adr = 0;
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$readmemh("c:/cores5/ft64/trunk/rtl/fpUnit/fpMul_tv.txt", mem);
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$readmemh("c:/cores5/ft64/trunk/rtl/fpUnit/fpMul_tv.txt", mem);
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$readmemh("c:/cores5/ft64/trunk/rtl/fpUnit/fpMul_tvd.txt", memd);
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#20 rst = 1;
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#20 rst = 1;
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#50 rst = 0;
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#50 rst = 0;
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end
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end
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always #5
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always #5
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clk = ~clk;
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clk = ~clk;
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delay5 #(32) u2 (clk, 1'b1, a, a5);
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delay5 #(32) u2 (clk, 1'b1, a, a5);
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delay5 #(32) u3 (clk, 1'b1, b, b5);
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delay5 #(32) u3 (clk, 1'b1, b, b5);
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delay5 #(64) u4 (clk, 1'b1, ad, ad5);
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delay5 #(64) u5 (clk, 1'b1, bd, bd5);
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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adr = 0;
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adr = 0;
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else
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else
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begin
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begin
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adr <= adr + 1;
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adr <= adr + 1;
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a <= mem[adr][31: 0];
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a <= mem[adr][31: 0];
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b <= mem[adr][63:32];
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b <= mem[adr][63:32];
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a6 <= a5;
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ad <= memd[adr][63: 0];
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b6 <= b5;
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bd <= memd[adr][127:64];
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if (adr > 5)
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if (adr > 5) begin
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memo[adr-6] <= {o,b5,a5};
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memo[adr-6] <= {o,b5,a5};
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memdo[adr-6] <= {od,bd5,ad5};
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end
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if (adr==8191) begin
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if (adr==8191) begin
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$writememh("c:/cores5/ft64/trunk/rtl/fpUnit/fpMul_tvo.txt", memo);
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$writememh("c:/cores5/ft64/trunk/rtl/fpUnit/fpMul_tvo.txt", memo);
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$writememh("c:/cores5/ft64/trunk/rtl/fpUnit/fpMul_tvdo.txt", memdo);
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$finish;
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$finish;
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end
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end
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end
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end
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fpMulnr #(32) u1 (clk, 1'b1, a, b, o, 3'b000);//, sign_exe, inf, overflow, underflow);
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fpMulnr #(32) u1 (clk, 1'b1, a, b, o, 3'b000);//, sign_exe, inf, overflow, underflow);
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fpMulnr #(64) u6 (clk, 1'b1, ad, bd, od, 3'b000);//, sign_exe, inf, overflow, underflow);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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