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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2016 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpNormalize.v
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// fpNormalize.v
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localparam EMSB = WID==128 ? 14 :
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==52 ? 39 :
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WID==48 ? 35 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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WID==24 ? 15 : 9;
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wire rbit = i[FMSB-1];
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wire rbit = i[FMSB-1];
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wire sbit = |i[FMSB-2:0];
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wire sbit = |i[FMSB-2:0];
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// shift mantissa left by one to reduce to a single whole digit
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// shift mantissa left by one to reduce to a single whole digit
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// if there is no exponent increment
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// if there is no exponent increment
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wire [FMSB+4:0] mo;
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wire [FMSB+4:0] mo;
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wire [FMSB+4:0] mo1 = xInf1 & incExp1 ? 0 :
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wire [FMSB+4:0] mo1 = (xInf1 & incExp1) ? 0 :
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incExp1 ? {i[FX:FMSB+2],gbit,rbit,sbit} : // reduce mantissa size
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incExp1 ? {i[FX:FMSB+2],gbit,rbit,sbit} : // reduce mantissa size
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{i[FX-1:FMSB+1],gbit,rbit,sbit}; // reduce mantissa size
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{i[FX-1:FMSB+1],gbit,rbit,sbit}; // reduce mantissa size
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wire [FMSB+3:0] mo2;
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wire [FMSB+3:0] mo2;
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wire [7:0] leadingZeros2;
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wire [7:0] leadingZeros2;
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generate
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generate
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begin
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begin
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if (WID==32)
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if (WID==32) begin
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
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assign leadingZeros2[7:6] = 2'b00;
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end
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else if (WID==128)
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else if (WID==128)
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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else if (WID==96)
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else if (WID==96)
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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else if (WID==80)
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else if (WID==80)
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// compensate for leadingZeros delay
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// compensate for leadingZeros delay
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wire xInf2;
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wire xInf2;
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delay1 #(EMSB+1) d2(.clk(clk), .ce(ce), .i(xo1), .o(xo2) );
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delay1 #(EMSB+1) d2(.clk(clk), .ce(ce), .i(xo1), .o(xo2) );
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delay1 #(1) d3(.clk(clk), .ce(ce), .i(xInf1), .o(xInf2) );
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delay1 #(1) d3(.clk(clk), .ce(ce), .i(xInf1), .o(xInf2) );
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// If the exponent underflowed, then the shift direction must be to the
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// If the exponent underflowed, then the shift direction must be to the
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// right regardless of mantissa bits; the number is denormalized.
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// right regardless of mantissa bits; the number is denormalized.
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// Otherwise the shift direction must be to the left.
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// Otherwise the shift direction must be to the left.
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wire rightOrLeft2; // 0=left,1=right
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wire rightOrLeft2; // 0=left,1=right
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delay1 #(1) d8(.clk(clk), .ce(ce), .i(under), .o(rightOrLeft2) );
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delay1 #(1) d8(.clk(clk), .ce(ce), .i(under), .o(rightOrLeft2) );
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// compute amount to shift right
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// compute amount to shift right
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// at infinity the exponent can't be incremented, so we can't shift right
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// at infinity the exponent can't be incremented, so we can't shift right
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// otherwise it was an underflow situation so the exponent was negative
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// otherwise it was an underflow situation so the exponent was negative
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// shift amount needs to be negated for shift register
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// shift amount needs to be negated for shift register
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wire [7:0] rshiftAmt2 = xInf2 ? 0 : -xo2 > FMSB+3 ? FMSB+4 : FMSB+4+xo2; // xo2 is negative !
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wire [7:0] rshiftAmt2 = xInf2 ? 0 : (($unsigned(-xo2) > $unsigned(FMSB+3)) ? FMSB+4 : -xo2);//FMSB+4+xo2; // xo2 is negative !
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// sign
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// sign
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// the output sign is the same as the input sign
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// the output sign is the same as the input sign
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delay1 #(1) d7(.clk(clk), .ce(ce), .i(so1), .o(so) );
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delay1 #(1) d7(.clk(clk), .ce(ce), .i(so1), .o(so) );
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wire [FMSB+3:0] mo2a;
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wire [FMSB+3:0] mo2a;
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//shiftAndMask #(FMSB+4) u1 (.op({rightOrLeft2,1'b0}), .a(mo2), .b(rightOrLeft2 ? lshiftAmt2 : rshiftAmt2), .mb(6'd0), .me(FMSB+3), .o(mo2a) );
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//shiftAndMask #(FMSB+4) u1 (.op({rightOrLeft2,1'b0}), .a(mo2), .b(rightOrLeft2 ? lshiftAmt2 : rshiftAmt2), .mb(6'd0), .me(FMSB+3), .o(mo2a) );
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// always @(posedge clk)
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// always @(posedge clk)
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// if (ce)
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// if (ce)
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assign mo = rightOrLeft2 ? mo2 >> rshiftAmt2 : mo2 << lshiftAmt2;
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assign mo = rightOrLeft2 ? (mo2 >> rshiftAmt2) : (mo2 << lshiftAmt2);
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//always @(posedge clk)
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// $display("%c xo2=%d -xo2=%d rshift=%d >%d %d", rightOrLeft2 ? "r" : "l",xo2, -xo2, rshiftAmt2,($unsigned(-xo2) > $unsigned(FMSB+3)),FMSB+3);
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assign o = {so,xo,mo[FMSB+4:1]};
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assign o = {so,xo,mo[FMSB+4:1]};
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endmodule
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endmodule
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