Line 110... |
Line 110... |
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
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assign leadingZeros2[7:6] = 2'b00;
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assign leadingZeros2[7:6] = 2'b00;
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end
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end
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else if (WID==128)
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else if (WID==128)
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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else if (WID==96)
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else if (WID==96) begin
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assign leadingZeros2[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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else if (WID==80)
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end
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else if (WID==80) begin
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assign leadingZeros2[7] = 1'b0;
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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else if (WID==64)
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end
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else if (WID==64) begin
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assign leadingZeros2[7] = 1'b0;
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo1,8'h0}), .o(leadingZeros2) );
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo1,8'h0}), .o(leadingZeros2) );
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end
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end
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end
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endgenerate
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endgenerate
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// compensate for leadingZeros delay
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// compensate for leadingZeros delay
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wire xInf2;
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wire xInf2;
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delay1 #(EMSB+1) d2(.clk(clk), .ce(ce), .i(xo1), .o(xo2) );
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delay1 #(EMSB+1) d2(.clk(clk), .ce(ce), .i(xo1), .o(xo2) );
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