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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpNormalize.v] - Diff between revs 10 and 11

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Rev 10 Rev 11
Line 110... Line 110...
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
assign leadingZeros2[7:6] = 2'b00;
assign leadingZeros2[7:6] = 2'b00;
end
end
else if (WID==128)
else if (WID==128)
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
else if (WID==96)
else if (WID==96) begin
 
assign leadingZeros2[7] = 1'b0;
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
else if (WID==80)
end
 
else if (WID==80) begin
 
assign leadingZeros2[7] = 1'b0;
cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
else if (WID==64)
end
 
else if (WID==64) begin
 
assign leadingZeros2[7] = 1'b0;
cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo1,8'h0}), .o(leadingZeros2) );
cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo1,8'h0}), .o(leadingZeros2) );
end
end
 
end
endgenerate
endgenerate
 
 
// compensate for leadingZeros delay
// compensate for leadingZeros delay
wire xInf2;
wire xInf2;
delay1 #(EMSB+1) d2(.clk(clk), .ce(ce), .i(xo1), .o(xo2) );
delay1 #(EMSB+1) d2(.clk(clk), .ce(ce), .i(xo1), .o(xo2) );

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