| Line 104... |
Line 104... |
wire [FMSB+3:0] mo2;
|
wire [FMSB+3:0] mo2;
|
wire [7:0] leadingZeros2;
|
wire [7:0] leadingZeros2;
|
|
|
generate
|
generate
|
begin
|
begin
|
if (WID==32) begin
|
if (WID <= 32) begin
|
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
|
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
|
assign leadingZeros2[7:6] = 2'b00;
|
assign leadingZeros2[7:6] = 2'b00;
|
end
|
end
|
else if (WID==128)
|
else if (WID==128)
|
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
|
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
|
| Line 144... |
Line 144... |
|
|
// compute amount to shift right
|
// compute amount to shift right
|
// at infinity the exponent can't be incremented, so we can't shift right
|
// at infinity the exponent can't be incremented, so we can't shift right
|
// otherwise it was an underflow situation so the exponent was negative
|
// otherwise it was an underflow situation so the exponent was negative
|
// shift amount needs to be negated for shift register
|
// shift amount needs to be negated for shift register
|
wire [7:0] rshiftAmt2 = xInf2 ? 0 : (($unsigned(-xo2) > $unsigned(FMSB+3)) ? FMSB+4 : -xo2);//FMSB+4+xo2; // xo2 is negative !
|
wire [7:0] rshiftAmt2 = xInf2 ? 0 : $signed(xo2) > 0 ? 0 : ~xo2+1;//FMSB+4+xo2; // xo2 is negative !
|
|
|
|
|
// sign
|
// sign
|
// the output sign is the same as the input sign
|
// the output sign is the same as the input sign
|
delay1 #(1) d7(.clk(clk), .ce(ce), .i(so1), .o(so) );
|
delay1 #(1) d7(.clk(clk), .ce(ce), .i(so1), .o(so) );
|
