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Line 90... |
wire [EMSB:0] xo1 = xo1a + incExp1;
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wire [EMSB:0] xo1 = xo1a + incExp1;
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wire [EMSB:0] xo2;
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wire [EMSB:0] xo2;
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wire xInf1 = &xo1;
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wire xInf1 = &xo1;
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// If infinity is reached then set the mantissa to zero
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// If infinity is reached then set the mantissa to zero
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wire gbit = i[FMSB];
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wire rbit = i[FMSB-1];
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wire sbit = |i[FMSB-2:0];
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// shift mantissa left by one to reduce to a single whole digit
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// shift mantissa left by one to reduce to a single whole digit
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// if there is no exponent increment
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// if there is no exponent increment
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wire [FMSB+4:0] mo;
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wire [FMSB+4:0] mo;
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wire [FMSB+4:0] mo1 = (xInf1 & incExp1) ? 0 :
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wire [FMSB+4:0] mo1 = (xInf1 & incExp1) ? 0 :
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incExp1 ? {i[FX:FMSB+2],gbit,rbit,sbit} : // reduce mantissa size
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incExp1 ? {i[FX:FMSB+1],|i[FMSB:0],1'b0} : // reduce mantissa size
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{i[FX-1:FMSB+1],gbit,rbit,sbit}; // reduce mantissa size
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{i[FX-1:FMSB],|i[FMSB-1:0],1'b0}; // reduce mantissa size
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wire [FMSB+3:0] mo2;
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wire [FMSB+4:0] mo2;
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wire [7:0] leadingZeros2;
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wire [7:0] leadingZeros2;
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generate
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generate
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begin
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begin
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if (WID <= 32) begin
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if (WID <= 32) begin
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
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assign leadingZeros2[7:6] = 2'b00;
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assign leadingZeros2[7:6] = 2'b00;
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end
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end
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else if (WID==128)
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else if (WID<=64) begin
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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else if (WID==96) begin
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assign leadingZeros2[7] = 1'b0;
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assign leadingZeros2[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo1,8'h0}), .o(leadingZeros2) );
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end
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end
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else if (WID==80) begin
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else if (WID<=80) begin
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assign leadingZeros2[7] = 1'b0;
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assign leadingZeros2[7] = 1'b0;
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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end
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end
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else if (WID==64) begin
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else if (WID<=96) begin
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assign leadingZeros2[7] = 1'b0;
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assign leadingZeros2[7] = 1'b0;
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo1,8'h0}), .o(leadingZeros2) );
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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end
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end
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else if (WID<=128)
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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end
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end
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endgenerate
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endgenerate
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// compensate for leadingZeros delay
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// compensate for leadingZeros delay
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wire xInf2;
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wire xInf2;
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