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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpNormalize.v
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// fpNormalize.v
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// to be negative. A right shift is needed.
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// to be negative. A right shift is needed.
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// ============================================================================
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// ============================================================================
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module fpNormalize(clk, ce, under, i, o);
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module fpNormalize(clk, ce, under, i, o);
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parameter WID = 128;
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parameter WID = 128;
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localparam MSB = WID-1;
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`include "fpSize.sv"
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input clk;
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input clk;
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input ce;
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input ce;
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input under;
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input under;
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input [EX:0] i; // expanded format input
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input [EX:0] i; // expanded format input
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// variables
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// variables
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wire so;
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wire so;
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wire so1 = i[EX]; // sign doesn't change
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wire so1 = i[EX]; // sign doesn't change
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// Since the there are *two* whole digits in the incoming format
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// Since the there are *three* whole digits in the incoming format
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// the number of whole digits needs to be reduced. If the MSB is
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// the number of whole digits needs to be reduced. If the MSB is
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// set, then increment the exponent and no shift is needed.
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// set, then increment the exponent and no shift is needed.
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wire [EMSB:0] xo;
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wire [EMSB:0] xo;
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wire [EMSB:0] xo1a = i[EX-1:FX+1];
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wire [EMSB:0] xo1a = i[EX-1:FX+1];
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wire xInf = &xo1a & !under;
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wire xInf = &xo1a & !under;
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wire incExp1 = !xInf & i[FX];
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wire xInf3 = &xo1a[EMSB:1] & !under;
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wire [EMSB:0] xo1 = xo1a + incExp1;
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wire incExp2 = !xInf3 & i[FX];
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wire incExp1 = !xInf & i[FX-1];
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wire [EMSB:0] xo1 = xo1a + (incExp2 ? 2'd2 : incExp1 ? 2'd1 : 2'd0);
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wire [EMSB:0] xo2;
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wire [EMSB:0] xo2;
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wire xInf1 = &xo1;
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wire xInf1 = &xo1;
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// If infinity is reached then set the mantissa to zero
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// If infinity is reached then set the mantissa to zero
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// shift mantissa left by one to reduce to a single whole digit
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// shift mantissa left by one to reduce to a single whole digit
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// if there is no exponent increment
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// if there is no exponent increment
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wire [FMSB+4:0] mo;
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wire [FMSB+4:0] mo;
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wire [FMSB+4:0] mo1 = (xInf1 & incExp1) ? 0 :
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wire [FMSB+4:0] mo1 = ((xInf1 & (incExp1|incExp2))|(xInf3 & incExp2)) ? 0 :
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incExp1 ? {i[FX:FMSB+1],|i[FMSB:0],1'b0} : // reduce mantissa size
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incExp2 ? {i[FX:FMSB+1],|i[FMSB:0]} :
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{i[FX-1:FMSB],|i[FMSB-1:0],1'b0}; // reduce mantissa size
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incExp1 ? {i[FX-1:FMSB],|i[FMSB-1:0]} : // reduce mantissa size
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{i[FX-2:FMSB-1],|i[FMSB-2:0]}; // reduce mantissa size
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wire [FMSB+4:0] mo2;
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wire [FMSB+4:0] mo2;
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wire [7:0] leadingZeros2;
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wire [7:0] leadingZeros2;
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generate
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generate
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begin
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begin
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end
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end
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else if (WID<=80) begin
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else if (WID<=80) begin
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assign leadingZeros2[7] = 1'b0;
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assign leadingZeros2[7] = 1'b0;
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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end
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end
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else if (WID<=84) begin
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assign leadingZeros2[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,24'b0}), .o(leadingZeros2) );
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end
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else if (WID<=96) begin
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else if (WID<=96) begin
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assign leadingZeros2[7] = 1'b0;
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assign leadingZeros2[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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end
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end
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else if (WID<=128)
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else if (WID<=128)
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