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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpNormalize.v
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// fpNormalize.v
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// - floating point normalization unit
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// - floating point normalization unit
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// - one cycle latency
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// - eight cycle latency
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// - parameterized width
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// - parameterized width
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// - IEEE 754 representation
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// - IEEE 754 representation
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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//
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//
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// On an underflowed input, the incoming exponent is assumed
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// On an underflowed input, the incoming exponent is assumed
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// to be negative. A right shift is needed.
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// to be negative. A right shift is needed.
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// ============================================================================
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// ============================================================================
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module fpNormalize(clk, ce, under, i, o);
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module fpNormalize(clk, ce, i, o, under_i, under_o, inexact_o);
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parameter WID = 128;
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parameter WID = 84;
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`include "fpSize.sv"
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`include "fpSize.sv"
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input clk;
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input clk;
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input ce;
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input ce;
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input under;
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input [EX:0] i; // expanded format input
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input [EX:0] i; // expanded format input
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output [WID+2:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit
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output [WID+2:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit
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input under_i;
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// variables
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output under_o;
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wire so;
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output inexact_o;
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wire so1 = i[EX]; // sign doesn't change
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// ----------------------------------------------------------------------------
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// No Clock required
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// ----------------------------------------------------------------------------
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reg [EMSB:0] xo0;
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reg so0;
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always @*
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xo0 <= i[EX-1:FX+1];
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always @*
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so0 <= i[EX]; // sign doesn't change
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// ----------------------------------------------------------------------------
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// Clock #1
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// - Capture exponent information
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// ----------------------------------------------------------------------------
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reg xInf1a, xInf1b, xInf1c;
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wire [FX:0] i1;
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delay1 #(FX+1) u11 (.clk(clk), .ce(ce), .i(i), .o(i1));
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always @(posedge clk)
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if (ce) xInf1a <= &xo0 & !under_i;
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always @(posedge clk)
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if (ce) xInf1b <= &xo0[EMSB:1] & !under_i;
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always @(posedge clk)
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if (ce) xInf1c = &xo0;
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// ----------------------------------------------------------------------------
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// Clock #2
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// - determine exponent increment
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// Since the there are *three* whole digits in the incoming format
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// Since the there are *three* whole digits in the incoming format
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// the number of whole digits needs to be reduced. If the MSB is
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// the number of whole digits needs to be reduced. If the MSB is
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// set, then increment the exponent and no shift is needed.
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// set, then increment the exponent and no shift is needed.
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wire [EMSB:0] xo;
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// ----------------------------------------------------------------------------
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wire [EMSB:0] xo1a = i[EX-1:FX+1];
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wire xInf2c, xInf2b;
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wire xInf = &xo1a & !under;
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wire xInf3 = &xo1a[EMSB:1] & !under;
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wire incExp2 = !xInf3 & i[FX];
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wire incExp1 = !xInf & i[FX-1];
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wire [EMSB:0] xo1 = xo1a + (incExp2 ? 2'd2 : incExp1 ? 2'd1 : 2'd0);
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wire [EMSB:0] xo2;
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wire [EMSB:0] xo2;
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wire xInf1 = &xo1;
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reg incExpByOne2, incExpByTwo2;
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delay1 u21 (.clk(clk), .ce(ce), .i(xInf1c), .o(xInf2c));
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// If infinity is reached then set the mantissa to zero
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delay1 u22 (.clk(clk), .ce(ce), .i(xInf1b), .o(xInf2b));
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// shift mantissa left by one to reduce to a single whole digit
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delay2 #(EMSB+1) u23 (.clk(clk), .ce(ce), .i(xo0), .o(xo2));
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// if there is no exponent increment
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delay2 u24 (.clk(clk), .ce(ce), .i(under_i), .o(under2));
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wire [FMSB+4:0] mo;
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wire [FMSB+4:0] mo1 = ((xInf1 & (incExp1|incExp2))|(xInf3 & incExp2)) ? 0 :
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always @(posedge clk)
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incExp2 ? {i[FX:FMSB+1],|i[FMSB:0]} :
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if (ce) incExpByTwo2 <= !xInf1b & i1[FX];
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incExp1 ? {i[FX-1:FMSB],|i[FMSB-1:0]} : // reduce mantissa size
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always @(posedge clk)
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{i[FX-2:FMSB-1],|i[FMSB-2:0]}; // reduce mantissa size
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if (ce) incExpByOne2 <= !xInf1a & i1[FX-1];
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wire [FMSB+4:0] mo2;
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wire [7:0] leadingZeros2;
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// ----------------------------------------------------------------------------
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// Clock #3
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// - increment exponent
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// - detect a zero mantissa
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// ----------------------------------------------------------------------------
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wire incExpByTwo3;
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wire incExpByOne3;
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wire [FX:0] i3;
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reg [EMSB:0] xo3;
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reg zeroMan3;
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delay1 u31 (.clk(clk), .ce(ce), .i(incExpByTwo2), .o(incExpByTwo3));
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delay1 u32 (.clk(clk), .ce(ce), .i(incExpByOne2), .o(incExpByOne3));
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delay3 #(FX+1) u33 (.clk(clk), .ce(ce), .i(i[FX:0]), .o(i3));
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wire [EMSB+1:0] xv3a = xo2 + {incExpByTwo2,1'b0};
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wire [EMSB+1:0] xv3b = xo2 + incExpByOne2;
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always @(posedge clk)
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if (ce) xo3 <= xo2 + (incExpByTwo2 ? 2'd2 : incExpByOne2 ? 2'd1 : 2'd0);
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always @(posedge clk)
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if(ce) zeroMan3 <= ((xv3b[EMSB+1]|| &xv3b[EMSB:0])||(xv3a[EMSB+1]| &xv3a[EMSB:0]))
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&& !under2 && !xInf2c;
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// ----------------------------------------------------------------------------
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// Clock #4
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// - Shift mantissa left
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// - If infinity is reached then set the mantissa to zero
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// shift mantissa left to reduce to a single whole digit
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// - create sticky bit
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// ----------------------------------------------------------------------------
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reg [FMSB+4:0] mo4;
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reg inexact4;
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always @(posedge clk)
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if(ce)
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casez({zeroMan3,incExpByTwo3,incExpByOne3})
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3'b1??: mo4 <= 1'd0;
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3'b01?: mo4 <= {i3[FX:FMSB+1],|i3[FMSB:0]};
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3'b001: mo4 <= {i3[FX-1:FMSB],|i3[FMSB-1:0]};
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default: mo4 <= {i3[FX-2:FMSB-1],|i3[FMSB-2:0]};
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endcase
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always @(posedge clk)
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if(ce)
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casez({zeroMan3,incExpByTwo3,incExpByOne3})
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3'b1??: inexact4 <= 1'd0;
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3'b01?: inexact4 <= |i3[FMSB:0];
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3'b001: inexact4 <= |i3[FMSB-1:0];
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default: inexact4 <= |i3[FMSB-2:0];
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endcase
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// ----------------------------------------------------------------------------
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// Clock edge #5
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// - count leading zeros
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// ----------------------------------------------------------------------------
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wire [7:0] leadingZeros5;
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wire [EMSB:0] xo5;
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wire xInf5;
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delay2 #(EMSB+1) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5));
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delay3 #(1) u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) );
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generate
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generate
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begin
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begin
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if (WID <= 32) begin
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if (WID <= 32) begin
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,5'b0}), .o(leadingZeros5) );
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assign leadingZeros2[7:6] = 2'b00;
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assign leadingZeros5[7:6] = 2'b00;
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end
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end
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else if (WID<=64) begin
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else if (WID<=64) begin
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assign leadingZeros2[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo1,8'h0}), .o(leadingZeros2) );
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,8'h0}), .o(leadingZeros5) );
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end
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end
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else if (WID<=80) begin
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else if (WID<=80) begin
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assign leadingZeros2[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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end
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end
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else if (WID<=84) begin
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else if (WID<=84) begin
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assign leadingZeros2[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,24'b0}), .o(leadingZeros2) );
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,24'b0}), .o(leadingZeros5) );
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end
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end
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else if (WID<=96) begin
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else if (WID<=96) begin
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assign leadingZeros2[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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end
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end
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else if (WID<=128)
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else if (WID<=128)
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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end
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end
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endgenerate
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endgenerate
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// compensate for leadingZeros delay
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wire xInf2;
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delay1 #(EMSB+1) d2(.clk(clk), .ce(ce), .i(xo1), .o(xo2) );
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delay1 #(1) d3(.clk(clk), .ce(ce), .i(xInf1), .o(xInf2) );
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// ----------------------------------------------------------------------------
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// Clock edge #6
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// - Compute how much we want to decrement exponent by
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// - compute amount to shift left and right
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// - at infinity the exponent can't be incremented, so we can't shift right
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// otherwise it was an underflow situation so the exponent was negative
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// shift amount needs to be negated for shift register
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// If the exponent underflowed, then the shift direction must be to the
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// If the exponent underflowed, then the shift direction must be to the
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// right regardless of mantissa bits; the number is denormalized.
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// right regardless of mantissa bits; the number is denormalized.
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// Otherwise the shift direction must be to the left.
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// Otherwise the shift direction must be to the left.
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wire rightOrLeft2; // 0=left,1=right
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// ----------------------------------------------------------------------------
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delay1 #(1) d8(.clk(clk), .ce(ce), .i(under), .o(rightOrLeft2) );
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reg [7:0] lshiftAmt6;
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reg [7:0] rshiftAmt6;
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wire rightOrLeft6; // 0=left,1=right
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wire xInf6;
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wire [EMSB:0] xo6;
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wire [FMSB+4:0] mo6;
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wire zeroMan6;
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vtdl #(1) u61 (.clk(clk), .ce(ce), .a(4'd5), .d(under_i), .q(rightOrLeft6) );
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delay1 #(EMSB+1) u62 (.clk(clk), .ce(ce), .i(xo5), .o(xo6));
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delay2 #(FMSB+5) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) );
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delay1 #(1) u64 (.clk(clk), .ce(ce), .i(xInf5), .o(xInf6) );
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delay3 u65 (.clk(clk), .ce(ce), .i(zeroMan3), .o(zeroMan6));
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always @(posedge clk)
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if (ce) lshiftAmt6 <= leadingZeros5 > xo5 ? xo5 : leadingZeros5;
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always @(posedge clk)
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if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : $signed(xo5) > 1'd0 ? 1'd0 : ~xo5+2'd1; // xo2 is negative !
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// ----------------------------------------------------------------------------
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// Clock edge #7
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// - fogure exponent
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// - shift mantissa
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// ----------------------------------------------------------------------------
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reg [EMSB:0] xo7;
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wire rightOrLeft7;
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reg [FMSB+4:0] mo7l, mo7r;
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delay1 u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .i(rightOrLeft7));
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always @(posedge clk)
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if (ce)
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xo7 <= zeroMan6 ? xo6 :
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xInf6 ? xo6 : // an infinite exponent is either a NaN or infinity; no need to change
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rightOrLeft6 ? 1'd0 : // on a right shift, the exponent was negative, it's being made to zero
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xo6 - lshiftAmt6; // on a left shift, the exponent can't be decremented below zero
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always @(posedge clk)
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if (ce) mo7r <= mo6 >> rshiftAmt6;
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always @(posedge clk)
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if (ce) mo7l <= mo6 << lshiftAmt6;
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// ----------------------------------------------------------------------------
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// Clock edge #8
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// - select mantissa
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// ----------------------------------------------------------------------------
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// Compute how much we want to decrement by
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wire so;
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wire [7:0] lshiftAmt2 = leadingZeros2 > xo2 ? xo2 : leadingZeros2;
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wire [EMSB:0] xo;
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reg [FMSB+4:0] mo;
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// compute amount to shift right
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vtdl #(1) u81 (.clk(clk), .ce(ce), .a(4'd7), .d(so0), .q(so) );
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// at infinity the exponent can't be incremented, so we can't shift right
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delay1 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xo7), .i(xo));
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// otherwise it was an underflow situation so the exponent was negative
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vtdl u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
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// shift amount needs to be negated for shift register
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delay1 u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
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wire [7:0] rshiftAmt2 = xInf2 ? 0 : $signed(xo2) > 0 ? 0 : ~xo2+1;//FMSB+4+xo2; // xo2 is negative !
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always @(posedge clk)
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if (ce) mo <= rightOrLeft7 ? mo7r : mo7l;
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// sign
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// the output sign is the same as the input sign
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delay1 #(1) d7(.clk(clk), .ce(ce), .i(so1), .o(so) );
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// exponent
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// always @(posedge clk)
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// if (ce)
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assign xo =
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xInf2 ? xo2 : // an infinite exponent is either a NaN or infinity; no need to change
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rightOrLeft2 ? 0 : // on a right shift, the exponent was negative, it's being made to zero
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xo2 - lshiftAmt2; // on a left shift, the exponent can't be decremented below zero
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// mantissa
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delay1 #(FMSB+5) d4(.clk(clk), .ce(ce), .i(mo1), .o(mo2) );
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wire [FMSB+3:0] mo2a;
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//shiftAndMask #(FMSB+4) u1 (.op({rightOrLeft2,1'b0}), .a(mo2), .b(rightOrLeft2 ? lshiftAmt2 : rshiftAmt2), .mb(6'd0), .me(FMSB+3), .o(mo2a) );
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// always @(posedge clk)
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// if (ce)
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assign mo = rightOrLeft2 ? (mo2 >> rshiftAmt2) : (mo2 << lshiftAmt2);
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//always @(posedge clk)
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// $display("%c xo2=%d -xo2=%d rshift=%d >%d %d", rightOrLeft2 ? "r" : "l",xo2, -xo2, rshiftAmt2,($unsigned(-xo2) > $unsigned(FMSB+3)),FMSB+3);
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assign o = {so,xo,mo[FMSB+4:1]};
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assign o = {so,xo,mo[FMSB+4:1]};
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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