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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpNormalize.v] - Diff between revs 26 and 27

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//     \/_//     robfinch<remove>@finitron.ca
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//       ||
//
//
//      fpNormalize.v
//      fpNormalize.v
//    - floating point normalization unit
//    - floating point normalization unit
//    - one cycle latency
//    - eight cycle latency
//    - parameterized width
//    - parameterized width
//    - IEEE 754 representation
//    - IEEE 754 representation
//
//
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
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//
//
// On an underflowed input, the incoming exponent is assumed
// On an underflowed input, the incoming exponent is assumed
// to be negative. A right shift is needed.
// to be negative. A right shift is needed.
// ============================================================================
// ============================================================================
 
 
module fpNormalize(clk, ce, under, i, o);
module fpNormalize(clk, ce, i, o, under_i, under_o, inexact_o);
parameter WID = 128;
parameter WID = 84;
`include "fpSize.sv"
`include "fpSize.sv"
 
 
input clk;
input clk;
input ce;
input ce;
input under;
 
input [EX:0] i;          // expanded format input
input [EX:0] i;          // expanded format input
output [WID+2:0] o;              // normalized output + guard, sticky and round bits, + 1 whole digit
output [WID+2:0] o;              // normalized output + guard, sticky and round bits, + 1 whole digit
 
input under_i;
// variables
output under_o;
wire so;
output inexact_o;
 
 
wire so1 = i[EX];               // sign doesn't change
 
 
// ----------------------------------------------------------------------------
 
// No Clock required
 
// ----------------------------------------------------------------------------
 
reg [EMSB:0] xo0;
 
reg so0;
 
 
 
always @*
 
        xo0 <= i[EX-1:FX+1];
 
always @*
 
        so0 <= i[EX];           // sign doesn't change
 
 
 
// ----------------------------------------------------------------------------
 
// Clock #1
 
// - Capture exponent information
 
// ----------------------------------------------------------------------------
 
reg xInf1a, xInf1b, xInf1c;
 
wire [FX:0] i1;
 
delay1 #(FX+1) u11 (.clk(clk), .ce(ce), .i(i), .o(i1));
 
 
 
always @(posedge clk)
 
        if (ce) xInf1a <= &xo0 & !under_i;
 
always @(posedge clk)
 
        if (ce) xInf1b <= &xo0[EMSB:1] & !under_i;
 
always @(posedge clk)
 
        if (ce) xInf1c = &xo0;
 
 
 
// ----------------------------------------------------------------------------
 
// Clock #2
 
// - determine exponent increment
// Since the there are *three* whole digits in the incoming format
// Since the there are *three* whole digits in the incoming format
// the number of whole digits needs to be reduced. If the MSB is
// the number of whole digits needs to be reduced. If the MSB is
// set, then increment the exponent and no shift is needed.
// set, then increment the exponent and no shift is needed.
wire [EMSB:0] xo;
// ----------------------------------------------------------------------------
wire [EMSB:0] xo1a = i[EX-1:FX+1];
wire xInf2c, xInf2b;
wire xInf = &xo1a & !under;
 
wire xInf3 = &xo1a[EMSB:1] & !under;
 
wire incExp2 = !xInf3 & i[FX];
 
wire incExp1 = !xInf & i[FX-1];
 
wire [EMSB:0] xo1 = xo1a + (incExp2 ? 2'd2 : incExp1 ? 2'd1 : 2'd0);
 
wire [EMSB:0] xo2;
wire [EMSB:0] xo2;
wire xInf1 = &xo1;
reg incExpByOne2, incExpByTwo2;
 
delay1 u21 (.clk(clk), .ce(ce), .i(xInf1c), .o(xInf2c));
// If infinity is reached then set the mantissa to zero
delay1 u22 (.clk(clk), .ce(ce), .i(xInf1b), .o(xInf2b));
// shift mantissa left by one to reduce to a single whole digit
delay2 #(EMSB+1) u23 (.clk(clk), .ce(ce), .i(xo0), .o(xo2));
// if there is no exponent increment
delay2 u24 (.clk(clk), .ce(ce), .i(under_i), .o(under2));
wire [FMSB+4:0] mo;
 
wire [FMSB+4:0] mo1 = ((xInf1 & (incExp1|incExp2))|(xInf3 & incExp2)) ? 0 :
always @(posedge clk)
        incExp2 ? {i[FX:FMSB+1],|i[FMSB:0]} :
        if (ce) incExpByTwo2 <= !xInf1b & i1[FX];
        incExp1 ? {i[FX-1:FMSB],|i[FMSB-1:0]} :  // reduce mantissa size
always @(posedge clk)
                         {i[FX-2:FMSB-1],|i[FMSB-2:0]};          // reduce mantissa size
        if (ce) incExpByOne2 <= !xInf1a & i1[FX-1];
wire [FMSB+4:0] mo2;
 
wire [7:0] leadingZeros2;
// ----------------------------------------------------------------------------
 
// Clock #3
 
// - increment exponent
 
// - detect a zero mantissa
 
// ----------------------------------------------------------------------------
 
 
 
wire incExpByTwo3;
 
wire incExpByOne3;
 
wire [FX:0] i3;
 
reg [EMSB:0] xo3;
 
reg zeroMan3;
 
delay1 u31 (.clk(clk), .ce(ce), .i(incExpByTwo2), .o(incExpByTwo3));
 
delay1 u32 (.clk(clk), .ce(ce), .i(incExpByOne2), .o(incExpByOne3));
 
delay3 #(FX+1) u33 (.clk(clk), .ce(ce), .i(i[FX:0]), .o(i3));
 
wire [EMSB+1:0] xv3a = xo2 + {incExpByTwo2,1'b0};
 
wire [EMSB+1:0] xv3b = xo2 + incExpByOne2;
 
 
 
always @(posedge clk)
 
        if (ce) xo3 <= xo2 + (incExpByTwo2 ? 2'd2 : incExpByOne2 ? 2'd1 : 2'd0);
 
 
 
always @(posedge clk)
 
        if(ce) zeroMan3 <= ((xv3b[EMSB+1]|| &xv3b[EMSB:0])||(xv3a[EMSB+1]| &xv3a[EMSB:0]))
 
                                                                                         && !under2 && !xInf2c;
 
 
 
// ----------------------------------------------------------------------------
 
// Clock #4
 
// - Shift mantissa left
 
// - If infinity is reached then set the mantissa to zero
 
//   shift mantissa left to reduce to a single whole digit
 
// - create sticky bit
 
// ----------------------------------------------------------------------------
 
 
 
reg [FMSB+4:0] mo4;
 
reg inexact4;
 
 
 
always @(posedge clk)
 
if(ce)
 
casez({zeroMan3,incExpByTwo3,incExpByOne3})
 
3'b1??: mo4 <= 1'd0;
 
3'b01?: mo4 <= {i3[FX:FMSB+1],|i3[FMSB:0]};
 
3'b001: mo4 <= {i3[FX-1:FMSB],|i3[FMSB-1:0]};
 
default:        mo4 <= {i3[FX-2:FMSB-1],|i3[FMSB-2:0]};
 
endcase
 
 
 
always @(posedge clk)
 
if(ce)
 
casez({zeroMan3,incExpByTwo3,incExpByOne3})
 
3'b1??: inexact4 <= 1'd0;
 
3'b01?: inexact4 <= |i3[FMSB:0];
 
3'b001: inexact4 <= |i3[FMSB-1:0];
 
default:        inexact4 <= |i3[FMSB-2:0];
 
endcase
 
 
 
// ----------------------------------------------------------------------------
 
// Clock edge #5
 
// - count leading zeros
 
// ----------------------------------------------------------------------------
 
wire [7:0] leadingZeros5;
 
wire [EMSB:0] xo5;
 
wire xInf5;
 
delay2 #(EMSB+1) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5));
 
delay3 #(1)      u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) );
 
 
generate
generate
begin
begin
if (WID <= 32) begin
if (WID <= 32) begin
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo1,5'b0}), .o(leadingZeros2) );
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,5'b0}), .o(leadingZeros5) );
assign leadingZeros2[7:6] = 2'b00;
assign leadingZeros5[7:6] = 2'b00;
end
end
else if (WID<=64) begin
else if (WID<=64) begin
assign leadingZeros2[7] = 1'b0;
assign leadingZeros5[7] = 1'b0;
cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo1,8'h0}), .o(leadingZeros2) );
cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,8'h0}), .o(leadingZeros5) );
end
end
else if (WID<=80) begin
else if (WID<=80) begin
assign leadingZeros2[7] = 1'b0;
assign leadingZeros5[7] = 1'b0;
cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
end
end
else if (WID<=84) begin
else if (WID<=84) begin
assign leadingZeros2[7] = 1'b0;
assign leadingZeros5[7] = 1'b0;
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,24'b0}), .o(leadingZeros2) );
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,24'b0}), .o(leadingZeros5) );
end
end
else if (WID<=96) begin
else if (WID<=96) begin
assign leadingZeros2[7] = 1'b0;
assign leadingZeros5[7] = 1'b0;
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
end
end
else if (WID<=128)
else if (WID<=128)
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo1,12'b0}), .o(leadingZeros2) );
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
end
end
endgenerate
endgenerate
 
 
// compensate for leadingZeros delay
 
wire xInf2;
 
delay1 #(EMSB+1) d2(.clk(clk), .ce(ce), .i(xo1), .o(xo2) );
 
delay1 #(1)      d3(.clk(clk), .ce(ce), .i(xInf1), .o(xInf2) );
 
 
 
 
 
 
// ----------------------------------------------------------------------------
 
// Clock edge #6
 
// - Compute how much we want to decrement exponent by
 
// - compute amount to shift left and right
 
// - at infinity the exponent can't be incremented, so we can't shift right
 
//   otherwise it was an underflow situation so the exponent was negative
 
//   shift amount needs to be negated for shift register
// If the exponent underflowed, then the shift direction must be to the
// If the exponent underflowed, then the shift direction must be to the
// right regardless of mantissa bits; the number is denormalized.
// right regardless of mantissa bits; the number is denormalized.
// Otherwise the shift direction must be to the left.
// Otherwise the shift direction must be to the left.
wire rightOrLeft2;      // 0=left,1=right
// ----------------------------------------------------------------------------
delay1 #(1) d8(.clk(clk), .ce(ce), .i(under), .o(rightOrLeft2) );
reg [7:0] lshiftAmt6;
 
reg [7:0] rshiftAmt6;
 
wire rightOrLeft6;      // 0=left,1=right
 
wire xInf6;
 
wire [EMSB:0] xo6;
 
wire [FMSB+4:0] mo6;
 
wire zeroMan6;
 
vtdl #(1) u61 (.clk(clk), .ce(ce), .a(4'd5), .d(under_i), .q(rightOrLeft6) );
 
delay1 #(EMSB+1) u62 (.clk(clk), .ce(ce), .i(xo5), .o(xo6));
 
delay2 #(FMSB+5) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) );
 
delay1 #(1)      u64 (.clk(clk), .ce(ce), .i(xInf5), .o(xInf6) );
 
delay3 u65 (.clk(clk), .ce(ce),  .i(zeroMan3), .o(zeroMan6));
 
 
 
always @(posedge clk)
 
        if (ce) lshiftAmt6 <= leadingZeros5 > xo5 ? xo5 : leadingZeros5;
 
 
 
always @(posedge clk)
 
        if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : $signed(xo5) > 1'd0 ? 1'd0 : ~xo5+2'd1;    // xo2 is negative !
 
 
 
// ----------------------------------------------------------------------------
 
// Clock edge #7
 
// - fogure exponent
 
// - shift mantissa
 
// ----------------------------------------------------------------------------
 
 
 
reg [EMSB:0] xo7;
 
wire rightOrLeft7;
 
reg [FMSB+4:0] mo7l, mo7r;
 
delay1 u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .i(rightOrLeft7));
 
 
 
always @(posedge clk)
 
if (ce)
 
        xo7 <= zeroMan6 ? xo6 :
 
                xInf6 ? xo6 :                                   // an infinite exponent is either a NaN or infinity; no need to change
 
                rightOrLeft6 ? 1'd0 :   // on a right shift, the exponent was negative, it's being made to zero
 
                xo6 - lshiftAmt6;                       // on a left shift, the exponent can't be decremented below zero
 
 
 
always @(posedge clk)
 
        if (ce) mo7r <= mo6 >> rshiftAmt6;
 
always @(posedge clk)
 
        if (ce) mo7l <= mo6 << lshiftAmt6;
 
 
 
 
 
// ----------------------------------------------------------------------------
 
// Clock edge #8
 
// - select mantissa
 
// ----------------------------------------------------------------------------
 
 
// Compute how much we want to decrement by
wire so;
wire [7:0] lshiftAmt2 = leadingZeros2 > xo2 ? xo2 : leadingZeros2;
wire [EMSB:0] xo;
 
reg [FMSB+4:0] mo;
// compute amount to shift right
vtdl #(1) u81 (.clk(clk), .ce(ce), .a(4'd7), .d(so0), .q(so) );
// at infinity the exponent can't be incremented, so we can't shift right
delay1 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xo7), .i(xo));
// otherwise it was an underflow situation so the exponent was negative
vtdl u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
// shift amount needs to be negated for shift register
delay1 u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
wire [7:0] rshiftAmt2 = xInf2 ? 0 : $signed(xo2) > 0 ? 0 : ~xo2+1;//FMSB+4+xo2;     // xo2 is negative !
 
 
 
 
always @(posedge clk)
 
        if (ce) mo <= rightOrLeft7 ? mo7r : mo7l;
 
 
// sign
 
// the output sign is the same as the input sign
 
delay1 #(1)      d7(.clk(clk), .ce(ce), .i(so1), .o(so) );
 
 
 
// exponent
 
//      always @(posedge clk)
 
//              if (ce)
 
assign xo =
 
                xInf2 ? xo2 :           // an infinite exponent is either a NaN or infinity; no need to change
 
                rightOrLeft2 ? 0 :       // on a right shift, the exponent was negative, it's being made to zero
 
                xo2 - lshiftAmt2;       // on a left shift, the exponent can't be decremented below zero
 
 
 
// mantissa
 
delay1 #(FMSB+5) d4(.clk(clk), .ce(ce), .i(mo1), .o(mo2) );
 
 
 
wire [FMSB+3:0] mo2a;
 
//shiftAndMask #(FMSB+4) u1 (.op({rightOrLeft2,1'b0}), .a(mo2), .b(rightOrLeft2 ? lshiftAmt2 : rshiftAmt2), .mb(6'd0), .me(FMSB+3), .o(mo2a) );
 
 
 
//      always @(posedge clk)
 
//              if (ce)
 
assign mo = rightOrLeft2 ? (mo2 >> rshiftAmt2) : (mo2 << lshiftAmt2);
 
//always @(posedge clk)
 
//      $display("%c xo2=%d -xo2=%d rshift=%d >%d %d", rightOrLeft2 ? "r" : "l",xo2, -xo2, rshiftAmt2,($unsigned(-xo2) > $unsigned(FMSB+3)),FMSB+3);
 
assign o = {so,xo,mo[FMSB+4:1]};
assign o = {so,xo,mo[FMSB+4:1]};
 
 
endmodule
endmodule
 
 
 
 
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