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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpRes.sv] - Diff between revs 15 and 26

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// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2019  Robert Finch, Waterloo
//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
//       ||
//       ||
//
//
//
//
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// You should have received a copy of the GNU General Public License
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see .
// along with this program.  If not, see .
//
//
// ============================================================================
// ============================================================================
//
//
module fpRes(clk, a, o);
module fpRes(clk, ce, a, o);
parameter WID = 128;
parameter WID = 128;
localparam MSB = WID-1;
`include "fpSize.sv"
localparam EMSB = WID==128 ? 14 :
 
                  WID==96 ? 14 :
 
                  WID==80 ? 14 :
 
                  WID==64 ? 10 :
 
                                  WID==52 ? 10 :
 
                                  WID==48 ? 11 :
 
                                  WID==44 ? 10 :
 
                                  WID==42 ? 10 :
 
                                  WID==40 ?  9 :
 
                                  WID==32 ?  7 :
 
                                  WID==24 ?  6 : 4;
 
localparam FMSB = WID==128 ? 111 :
 
                  WID==96 ? 79 :
 
                  WID==80 ? 63 :
 
                  WID==64 ? 51 :
 
                                  WID==52 ? 39 :
 
                                  WID==48 ? 34 :
 
                                  WID==44 ? 31 :
 
                                  WID==42 ? 29 :
 
                                  WID==40 ? 28 :
 
                                  WID==32 ? 22 :
 
                                  WID==24 ? 15 : 9;
 
input clk;
input clk;
 
input ce;
input [WID-1:0] a;
input [WID-1:0] a;
output [WID-1:0] o;
output [WID-1:0] o;
 
 
// This table encodes two endpoints k0, k1 of a piece-wise linear
// This table encodes two endpoints k0, k1 of a piece-wise linear
// approximation to the reciprocal in the range [1.0,2.0).
// approximation to the reciprocal in the range [1.0,2.0).
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wire [EMSB:0] exp3;
wire [EMSB:0] exp3;
wire [9:0] index = ma[FMSB:FMSB-9];
wire [9:0] index = ma[FMSB:FMSB-9];
reg [9:0] indexr;
reg [9:0] indexr;
reg [15:0] k0, k1;
reg [15:0] k0, k1;
always @(posedge clk)
always @(posedge clk)
        indexr <= index;
        if(ce) indexr <= index;
always @(posedge clk)
always @(posedge clk)
        k0 <= k01[indexr][31:16];
        if(ce) k0 <= k01[indexr][31:16];
always @(posedge clk)
always @(posedge clk)
        k1 <= k01[indexr][15: 0];
        if(ce) k1 <= k01[indexr][15: 0];
delay3 #(1) u2 (.clk(clk), .ce(1'b1), .i(sa), .o(sa3));
delay3 #(1) u2 (.clk(clk), .ce(1'b1), .i(sa), .o(sa3));
delay3 #(EMSB+1) u3 (.clk(clk), .ce(1'b1), .i(exp), .o(exp3));
delay3 #(EMSB+1) u3 (.clk(clk), .ce(1'b1), .i(exp), .o(exp3));
wire [15:0] eps = ma[FMSB-10:FMSB-10-15];
wire [15:0] eps = ma[FMSB-10:FMSB-10-15];
wire [31:0] p = k1 * eps;
wire [31:0] p = k1 * eps;
reg [15:0] r0;
reg [15:0] r0;
always @(posedge clk)
always @(posedge clk)
        r0 <= k0 - (p >> 26);
        if(ce) r0 <= k0 - (p >> 26);
assign o = {sa3,exp3,r0[14:0],{FMSB+2-16{1'b0}}};
assign o = {sa3,exp3,r0[14:0],{FMSB+2-16{1'b0}}};
 
 
always @*
always @*
        if (WID < 48) begin
        if (WID < 48) begin
                $display("Reciprocal estimate needs at least 48 bit floats.");
                $display("Reciprocal estimate needs at least 48 bit floats.");

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