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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpRound.v] - Diff between revs 10 and 13

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Rev 10 Rev 13
Line 74... Line 74...
reg rnd;
reg rnd;
 
 
// Compute the round bit
// Compute the round bit
// Infinities and NaNs are not rounded!
// Infinities and NaNs are not rounded!
always @(xInf,rm,g,r,s,so)
always @(xInf,rm,g,r,s,so)
        case ({xInf,rm})
        casez ({xInf,rm})
        3'd0:   rnd = (g & r) | (r & s);        // round to nearest even
        4'b0000:        rnd = (g & r) | (r & s);        // round to nearest even
        3'd1:   rnd = 0;                                 // round to zero (truncate)
        4'b0001:        rnd = 0;                                 // round to zero (truncate)
        3'd2:   rnd = (r | s) & !so;            // round towards +infinity
        4'b0010:        rnd = (r | s) & !so;            // round towards +infinity
        3'd3:   rnd = (r | s) & so;                     // round towards -infinity
        4'b0011:        rnd = (r | s) & so;                     // round towards -infinity
        3'd4:   rnd = (r | s);
        4'b1???:    rnd = (r | s);
        default:        rnd = 0;                         // no rounding if exponent indicates infinite or NaN
        default:        rnd = 0;                         // no rounding if exponent indicates infinite or NaN
        endcase
        endcase
 
 
// round the number, check for carry
// round the number, check for carry
// note: inf. exponent checked above (if the exponent was infinite already, then no rounding occurs as rnd = 0)
// note: inf. exponent checked above (if the exponent was infinite already, then no rounding occurs as rnd = 0)

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