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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2016 Robert Finch, Stratford
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// \\__/ o\ (C) 2006-2016 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpRound.v
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// - floating point rounding unit
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// - parameterized width
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// - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// fpRound.v
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// - floating point rounding unit
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// - parameterized width
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// - IEEE 754 representation
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//
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// This unit takes a normalized floating point number in an
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// expanded format and rounds it according to the IEEE-754
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// standard. NaN's and infinities are not rounded.
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// This module has a single cycle latency.
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//
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// Mode
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// 0: round to nearest even
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// 1: round to zero (truncate)
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// 2: round towards +infinity
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// 3: round towards -infinity
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// ============================================================================
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// ============================================================================
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//
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module fpRound(rm, i, o);
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module fpRound(rm, i, o);
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parameter WID = 32;
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parameter WID = 128;
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localparam MSB = WID-1;
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localparam MSB = WID-1;
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localparam EMSB = WID==80 ? 14 :
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 10 :
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WID==48 ? 10 :
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WID==44 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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WID==24 ? 6 : 4;
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localparam FMSB = WID==80 ? 63 :
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==52 ? 39 :
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WID==48 ? 35 :
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WID==48 ? 35 :
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WID==44 ? 31 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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WID==24 ? 15 : 9;
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input [2:0] rm; // rounding mode
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input [2:0] rm; // rounding mode
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input [WID+3:0] i; // intermediate format input
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input [MSB+3:0] i; // intermediate format input
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output [WID-1:0] o; // rounded output
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output [WID-1:0] o; // rounded output
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//------------------------------------------------------------
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//------------------------------------------------------------
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// variables
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// variables
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wire so;
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wire so;
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wire [EMSB:0] xo;
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wire [EMSB:0] xo;
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reg [FMSB:0] mo;
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reg [FMSB:0] mo;
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wire [EMSB:0] xo1 = i[EMSB+FMSB+5:FMSB+5];
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wire [EMSB:0] xo1 = i[MSB+2:FMSB+4];
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wire [FMSB+4:0] mo1 = i[FMSB+4:0];
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wire [FMSB+3:0] mo1 = i[FMSB+3:0];
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wire xInf = &xo1;
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wire xInf = &xo1;
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wire dn = !(|xo1); // denormalized input
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wire dn = !(|xo1); // denormalized input
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assign o = {so,xo,mo};
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assign o = {so,xo,mo};
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wire g = i[2]; // guard bit: always the same bit for all operations
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wire g = i[2]; // guard bit: always the same bit for all operations
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// Compute the round bit
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// Compute the round bit
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// Infinities and NaNs are not rounded!
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// Infinities and NaNs are not rounded!
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always @(xInf,rm,g,r,s,so)
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always @(xInf,rm,g,r,s,so)
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case ({xInf,rm})
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case ({xInf,rm})
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4'd0: rnd = (g & r) | (r & s); // round to nearest even
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3'd0: rnd = (g & r) | (r & s); // round to nearest even
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4'd1: rnd = 0; // round to zero (truncate)
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3'd1: rnd = 0; // round to zero (truncate)
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4'd2: rnd = (r | s) & !so; // round towards +infinity
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3'd2: rnd = (r | s) & !so; // round towards +infinity
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4'd3: rnd = (r | s) & so; // round towards -infinity
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3'd3: rnd = (r | s) & so; // round towards -infinity
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3'd4: rnd = (r | s);
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default: rnd = 0; // no rounding if exponent indicates infinite or NaN
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default: rnd = 0; // no rounding if exponent indicates infinite or NaN
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endcase
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endcase
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// round the number, check for carry
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// round the number, check for carry
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// note: inf. exponent checked above (if the exponent was infinite already, then no rounding occurs as rnd = 0)
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// note: inf. exponent checked above (if the exponent was infinite already, then no rounding occurs as rnd = 0)
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// note: exponent increments if there is a carry (can only increment to infinity)
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// note: exponent increments if there is a carry (can only increment to infinity)
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// performance note: use the carry chain to increment the exponent
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// performance note: use the carry chain to increment the exponent
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wire [MSB+2:0] rounded = {xo1,mo1[FMSB+4:2]} + rnd;
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wire [MSB:0] rounded = {xo1,mo1[FMSB+3:2]} + rnd;
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wire carry = mo1[FMSB+4] & !rounded[FMSB+2];
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wire carry = mo1[FMSB+3] & !rounded[FMSB+1];
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assign so = i[WID+3];
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assign so = i[MSB+3];
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assign xo = rounded[MSB+2:FMSB+3];
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assign xo = rounded[MSB:FMSB+2];
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always @(rnd or xo or carry or dn or rounded or mo1)
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always @(rnd or xo or carry or dn or rounded or mo1)
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casex({rnd,&xo,carry,dn})
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casex({rnd,&xo,carry,dn})
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4'b0xx0: mo = mo1[FMSB+3:3]; // not rounding, not denormalized, => hide MSB
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4'b0xx0: mo = mo1[FMSB+2:2]; // not rounding, not denormalized, => hide MSB
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4'b0xx1: mo = mo1[FMSB+4:4]; // not rounding, denormalized
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4'b0xx1: mo = mo1[FMSB+3:3]; // not rounding, denormalized
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4'b1000: mo = rounded[FMSB+1:1]; // exponent didn't change, number was normalized, => hide MSB
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4'b1000: mo = rounded[FMSB :0]; // exponent didn't change, number was normalized, => hide MSB
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4'b1001: mo = rounded[FMSB+2:2]; // exponent didn't change, but number was denormalized, => retain MSB
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4'b1001: mo = rounded[FMSB+1:1]; // exponent didn't change, but number was denormalized, => retain MSB
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4'b1010: mo = rounded[FMSB+2:2]; // exponent incremented (new MSB generated), number was normalized, => hide 'extra (FMSB+2)' MSB
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4'b1010: mo = rounded[FMSB+1:1]; // exponent incremented (new MSB generated), number was normalized, => hide 'extra (FMSB+2)' MSB
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4'b1011: mo = rounded[FMSB+2:2]; // exponent incremented (new MSB generated), number was denormalized, number became normalized, => hide 'extra (FMSB+2)' MSB
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4'b1011: mo = rounded[FMSB+1:1]; // exponent incremented (new MSB generated), number was denormalized, number became normalized, => hide 'extra (FMSB+2)' MSB
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4'b11xx: mo = 0; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite
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4'b11xx: mo = 0; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite
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endcase
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endcase
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endmodule
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endmodule
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// Round and register the output
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// Round and register the output
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module fpRoundReg(clk, ce, rm, i, o);
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module fpRoundReg(clk, ce, rm, i, o);
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parameter WID = 32;
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parameter WID = 128;
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localparam MSB = WID-1;
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localparam MSB = WID-1;
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localparam EMSB = WID==80 ? 14 :
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 10 :
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WID==48 ? 10 :
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WID==44 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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WID==24 ? 6 : 4;
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localparam FMSB = WID==80 ? 63 :
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==52 ? 39 :
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WID==48 ? 35 :
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WID==48 ? 35 :
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WID==44 ? 31 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==42 ? 29 :
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WID==32 ? 22 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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WID==24 ? 15 : 9;
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input clk;
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input clk;
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input ce;
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input ce;
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input [1:0] rm; // rounding mode
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input [2:0] rm; // rounding mode
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input [WID+2:0] i; // expanded format input
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input [MSB+3:0] i; // expanded format input
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output reg [WID-1:0] o; // rounded output
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output reg [WID-1:0] o; // rounded output
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wire [WID-1:0] o1;
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wire [WID-1:0] o1;
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fpRound #(WID) u1 (.rm(rm), .i(i), .o(o1) );
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fpRound #(WID) u1 (.rm(rm), .i(i), .o(o1) );
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if (ce)
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if (ce)
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o <= o1;
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o <= o1;
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endmodule
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endmodule
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module fpRound_tb();
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wire [31:0] o1,o2,o3,o4,o5,o6;
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fpRound u1 (3'd1, 36'h0, o1); // zero for zero
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fpRound u2 (3'd1, 36'h444444444, o2); //
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fpRound u3 (3'd1, 36'h444444444, o3); //
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endmodule
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