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Line 27... |
//
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//
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// Floating Point Multiplier / Divider
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// Floating Point Multiplier / Divider
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//
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//
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// ============================================================================
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// ============================================================================
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`include "fpConfig.sv"
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`include "fp_defines.v"
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`include "fp_defines.v"
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module fpSqrt(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
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module fpSqrt(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
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parameter WID = 128;
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parameter FPWID = 32;
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`include "fpSize.sv"
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`include "fpSize.sv"
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localparam pShiftAmt =
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FPWID==80 ? 48 :
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FPWID==64 ? 36 :
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FPWID==32 ? 7 : (FMSB+1-16);
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input rst;
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input rst;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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// - derive basic information
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// - derive basic information
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// - calculate exponent
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// - calculate exponent
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// - calculate fraction
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// - calculate fraction
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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fpDecomp #(WID) u1
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fpDecomp #(FPWID) u1
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(
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(
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.i(a),
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.i(a),
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.sgn(sa),
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.sgn(sa),
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.exp(xa),
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.exp(xa),
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.fract(fracta),
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.fract(fracta),
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| Line 98... |
Line 103... |
);
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);
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assign ex1 = xa + 8'd1;
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assign ex1 = xa + 8'd1;
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assign so = 1'b0; // square root of positive numbers only
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assign so = 1'b0; // square root of positive numbers only
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assign xo = (ex1 >> 1) + (bias >> 1); // divide by 2 cuts the bias in half, so 1/2 of it is added back in.
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assign xo = (ex1 >> 1) + (bias >> 1); // divide by 2 cuts the bias in half, so 1/2 of it is added back in.
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assign mo = aNan ? {1'b1,a[FMSB:0],{FMSB+1{1'b0}}} : (sqrto << 36);
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assign mo = aNan ? {1'b1,a[FMSB:0],{FMSB+1{1'b0}}} : (sqrto << pShiftAmt);
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assign sqrinf = aInf;
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assign sqrinf = aInf;
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assign sqrneg = !az & so;
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assign sqrneg = !az & so;
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wire [FMSB+2:0] fracta1 = ex1[0] ? {1'b0,fracta} << 1 : {2'b0,fracta};
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wire [FMSB+2:0] fracta1 = ex1[0] ? {1'b0,fracta} << 1 : {2'b0,fracta};
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Line 115... |
(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.ce(ce),
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.ce(ce),
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.ld(ld),
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.ld(ld),
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.a({fracta1,{FMSB+1{1'b0}}}),
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.a({1'b0,fracta1,{FMSB+1{1'b0}}}),
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.o(sqrto),
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.o(sqrto),
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.done(done)
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.done(done)
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);
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);
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always @*
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always @*
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endmodule
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endmodule
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module fpSqrtnr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg);
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module fpSqrtnr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg);
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parameter WID=32;
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parameter FPWID=32;
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`include "fpSize.sv"
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`include "fpSize.sv"
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input rst;
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input rst;
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input clk;
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input clk;
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input ce;
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input ce;
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Line 152... |
wire [EX:0] o1;
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wire [EX:0] o1;
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wire inf1;
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wire inf1;
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wire [MSB+3:0] fpn0;
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wire [MSB+3:0] fpn0;
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wire done1;
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wire done1;
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fpSqrt #(WID) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg);
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fpSqrt #(FPWID) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg);
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fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) );
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fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
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fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done));
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delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done));
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endmodule
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endmodule
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