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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpSqrt.v
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// fpSqrt.v
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//
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//
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// Floating Point Multiplier / Divider
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// Floating Point Multiplier / Divider
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//
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//
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// ============================================================================
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// ============================================================================
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module fpSqrt(rst, clk, ce, ld, a, o, done);
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`include "fp_defines.v"
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parameter WID = 128;
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localparam MSB = WID-1;
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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module fpSqrt(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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parameter WID = 128;
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`include "fpSize.sv"
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input rst;
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input rst;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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input [MSB:0] a;
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input [MSB:0] a;
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output [EX:0] o;
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output reg [EX:0] o;
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output done;
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output done;
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output sqrinf;
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output sqrneg;
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// registered outputs
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// registered outputs
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reg sign_exe;
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reg sign_exe;
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reg inf;
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reg inf;
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reg overflow;
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reg overflow;
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Line 99... |
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assign ex1 = xa + 8'd1;
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assign ex1 = xa + 8'd1;
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assign so = 1'b0; // square root of positive numbers only
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assign so = 1'b0; // square root of positive numbers only
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assign xo = (ex1 >> 1) + (bias >> 1); // divide by 2 cuts the bias in half, so 1/2 of it is added back in.
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assign xo = (ex1 >> 1) + (bias >> 1); // divide by 2 cuts the bias in half, so 1/2 of it is added back in.
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assign mo = aNan ? {1'b1,a[FMSB:0],{FMSB+1{1'b0}}} : (sqrto << 36);
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assign mo = aNan ? {1'b1,a[FMSB:0],{FMSB+1{1'b0}}} : (sqrto << 36);
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assign sqrinf = aInf;
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assign sqrneg = !az & so;
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wire [FMSB+2:0] fracta1 = ex1[0] ? {1'b0,fracta} << 1 : {2'b0,fracta};
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wire [FMSB+2:0] fracta1 = ex1[0] ? {1'b0,fracta} << 1 : {2'b0,fracta};
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isqrt #(FX+1) u2
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isqrt #(FX+1) u2
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(
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(
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.a({fracta1,{FMSB+1{1'b0}}}),
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.a({fracta1,{FMSB+1{1'b0}}}),
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.o(sqrto),
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.o(sqrto),
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.done(done)
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.done(done)
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);
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);
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assign o = aNan ? {sa,xa,mo} : {so,xo,mo};
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always @*
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casez({aNan,sqrinf,sqrneg})
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3'b1??: o <= {sa,xa,mo};
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3'b01?: o <= {sa,1'b1,qNaN|`QSQRTINF,{FMSB+1{1'b0}}};
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3'b001: o <= {sa,1'b1,qNaN|`QSQRTNEG,{FMSB+1{1'b0}}};
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default: o <= {so,xo,mo};
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endcase
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endmodule
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endmodule
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module fpSqrtnr(rst, clk, ce, ld, a, o, rm, done, inf);
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module fpSqrtnr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg);
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parameter WID=32;
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parameter WID=32;
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localparam MSB = WID-1;
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`include "fpSize.sv"
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input rst;
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input rst;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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input [MSB:0] a;
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input [MSB:0] a;
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output [MSB:0] o;
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output [MSB:0] o;
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input [2:0] rm;
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input [2:0] rm;
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output done;
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output done;
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output inf;
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output inf;
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output sqrinf;
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output sqrneg;
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wire [EX:0] o1;
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wire [EX:0] o1;
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wire inf1;
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wire inf1;
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wire [MSB+3:0] fpn0;
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wire [MSB+3:0] fpn0;
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wire done1;
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wire done1;
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fpSqrt #(WID) u1 (rst, clk, ce, ld, a, o1, done1);
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fpSqrt #(WID) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg);
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fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) );
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fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) );
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fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done));
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delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done));
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endmodule
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endmodule
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