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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpSqrt.v] - Diff between revs 26 and 28

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//                                                                          
//                                                                          
//      Floating Point Multiplier / Divider
//      Floating Point Multiplier / Divider
//
//
// ============================================================================
// ============================================================================
 
 
 
`include "fpConfig.sv"
`include "fp_defines.v"
`include "fp_defines.v"
 
 
module fpSqrt(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
module fpSqrt(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
parameter WID = 128;
parameter FPWID = 32;
`include "fpSize.sv"
`include "fpSize.sv"
 
localparam pShiftAmt =
 
        FPWID==80 ? 48 :
 
        FPWID==64 ? 36 :
 
        FPWID==32 ? 7 : (FMSB+1-16);
 
 
input rst;
input rst;
input clk;
input clk;
input ce;
input ce;
input ld;
input ld;
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// - derive basic information
// - derive basic information
// - calculate exponent
// - calculate exponent
// - calculate fraction
// - calculate fraction
// -----------------------------------------------------------
// -----------------------------------------------------------
 
 
fpDecomp #(WID) u1
fpDecomp #(FPWID) u1
(
(
        .i(a),
        .i(a),
        .sgn(sa),
        .sgn(sa),
        .exp(xa),
        .exp(xa),
        .fract(fracta),
        .fract(fracta),
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);
);
 
 
assign ex1 = xa + 8'd1;
assign ex1 = xa + 8'd1;
assign so = 1'b0;                               // square root of positive numbers only
assign so = 1'b0;                               // square root of positive numbers only
assign xo = (ex1 >> 1) + (bias >> 1);   // divide by 2 cuts the bias in half, so 1/2 of it is added back in.
assign xo = (ex1 >> 1) + (bias >> 1);   // divide by 2 cuts the bias in half, so 1/2 of it is added back in.
assign mo = aNan ? {1'b1,a[FMSB:0],{FMSB+1{1'b0}}} : (sqrto << 36);
assign mo = aNan ? {1'b1,a[FMSB:0],{FMSB+1{1'b0}}} : (sqrto << pShiftAmt);
assign sqrinf = aInf;
assign sqrinf = aInf;
assign sqrneg = !az & so;
assign sqrneg = !az & so;
 
 
wire [FMSB+2:0] fracta1 = ex1[0] ? {1'b0,fracta} << 1 : {2'b0,fracta};
wire [FMSB+2:0] fracta1 = ex1[0] ? {1'b0,fracta} << 1 : {2'b0,fracta};
 
 
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(
(
        .rst(rst),
        .rst(rst),
        .clk(clk),
        .clk(clk),
        .ce(ce),
        .ce(ce),
        .ld(ld),
        .ld(ld),
        .a({fracta1,{FMSB+1{1'b0}}}),
        .a({1'b0,fracta1,{FMSB+1{1'b0}}}),
        .o(sqrto),
        .o(sqrto),
        .done(done)
        .done(done)
);
);
 
 
always @*
always @*
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endmodule
endmodule
 
 
module fpSqrtnr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg);
module fpSqrtnr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg);
parameter WID=32;
parameter FPWID=32;
`include "fpSize.sv"
`include "fpSize.sv"
 
 
input rst;
input rst;
input clk;
input clk;
input ce;
input ce;
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wire [EX:0] o1;
wire [EX:0] o1;
wire inf1;
wire inf1;
wire [MSB+3:0] fpn0;
wire [MSB+3:0] fpn0;
wire done1;
wire done1;
 
 
fpSqrt      #(WID) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg);
fpSqrt      #(FPWID) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg);
fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) );
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
fpRoundReg  #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
fpRound  #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2          #(1)   u8(.clk(clk), .ce(ce), .i(done1), .o(done));
delay2          #(1)   u8(.clk(clk), .ce(ce), .i(done1), .o(done));
endmodule
endmodule
 
 
 
 
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