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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [fpZLUnit.v] - Diff between revs 9 and 26

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`timescale 1ns / 1ps
`timescale 1ns / 1ps
// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2007-2016  Robert Finch, Waterloo
//   \\__/ o\    (C) 2007-2019  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//       ||
//
//
//      fpZLUnit.v
//      fpZLUnit.v
Line 35... Line 35...
//      fman    - get mantissa (set exponent to zero)
//      fman    - get mantissa (set exponent to zero)
//  fcmp
//  fcmp
//
//
// ============================================================================
// ============================================================================
 
 
`define FLOAT   6'h36
`define FLOAT   4'h1
`define FMOV    6'h00
`define FLT1            4'h1
`define FNEG    6'h04
`define FLT2            4'h2
`define FABS    6'h05
`define FLT3            4'h3
`define FSIGN   6'h06
`define FANDI           4'hE
`define FMAN    6'h07
`define FORI            4'hF
`define FNABS   6'h08
 
`define FCVTSQ  6'h0B
`define FMAX            5'h10
 
`define FMIN            5'h11
 
`define FCMP    5'h06
 
`define FMOV    5'h00
 
`define FNEG    5'h04
 
`define FABS    5'h05
 
`define FSIGN   5'h06
 
`define FMAN    5'h07
 
`define FNABS   5'h08
 
`define FCVTSD  5'h09
 
`define F32TO80 5'h0A
 
`define ISNAN           5'h0E
 
`define CPYSGN  5'h0F   // FLT2
 
`define FINITE  5'h0F   // FLT1
 
//`define FCVTSQ  6'h1B
 
`define FCVTDS  5'h19
 
`define FSLT            5'h10
 
`define FSGE            5'h11
 
`define FSLE            5'h12
 
`define FSGT            5'h13
 
`define FSEQ            5'h14
 
`define FSNE            5'h15
 
`define FSUN            5'h16
 
`define F80TO32 5'h1A
 
`define UNORD           5'h1F
 
 
module fpZLUnit
module fpZLUnit
#(parameter WID=32)
#(parameter WID=80)
(
(
    input [31:0] ir,
  input [3:0] op4,
        input [WID-1:0] a,
  input [4:0] func5,
        input [WID-1:0] b,       // for fcmp
  input [39:0] ir,
        output reg [WID-1:0] o,
        input [WID+3:0] a,
        output nanx
        input [WID+3:0] b,       // for fcmp
 
        input [WID+3:0] c,       // for fcmp
 
        output reg [WID+3:0] o,
 
        output reg nanx
);
);
localparam MSB = WID-1;
`include "fpSize.sv"
localparam EMSB = WID==128 ? 14 :
 
                  WID==96 ? 14 :
 
                  WID==80 ? 14 :
 
                  WID==64 ? 10 :
 
                                  WID==52 ? 10 :
 
                                  WID==48 ? 10 :
 
                                  WID==44 ? 10 :
 
                                  WID==42 ? 10 :
 
                                  WID==40 ?  9 :
 
                                  WID==32 ?  7 :
 
                                  WID==24 ?  6 : 4;
 
localparam FMSB = WID==128 ? 111 :
 
                  WID==96 ? 79 :
 
                  WID==80 ? 63 :
 
                  WID==64 ? 51 :
 
                                  WID==52 ? 39 :
 
                                  WID==48 ? 35 :
 
                                  WID==44 ? 31 :
 
                                  WID==42 ? 29 :
 
                                  WID==40 ? 28 :
 
                                  WID==32 ? 22 :
 
                                  WID==24 ? 15 : 9;
 
 
 
wire [5:0] op = ir[5:0];
 
wire [1:0] prec = ir[28:27];
 
wire [5:0] fn = ir[17:12];
 
wire [2:0] fn3 = ir[31:29];
 
 
 
wire [3:0] cmp_o;
//wire [1:0] prec = ir[25:24];
 
 
fp_cmp_unit #(WID) u1 (.a(a), .b(b), .o(cmp_o), .nanx(nanx) );
wire nanxab,nanxac,nanxbc;
 
wire nana;
 
wire [EMSB:0] expa;
 
wire [FMSB:0] ma;
 
wire xinfa;
 
wire [4:0] cmp_o, cmpac_o, cmpbc_o;
 
 
 
// Zero is being passed for b in some cases so the NaN must come from a if
 
// present.
 
fp_cmp_unit #(WID+4) u1 (.a(a), .b(b), .o(cmp_o), .nanx(nanxab) );
 
fp_cmp_unit #(WID+4) u2 (.a(a), .b(c), .o(cmpac_o), .nanx(nanxac) );
 
fp_cmp_unit #(WID+4) u3 (.a(b), .b(c), .o(cmpbc_o), .nanx(nanxbc) );
 
fpDecomp #(WID+4) u4 (.i(a), .sgn(), .exp(expa), .man(ma), .fract(), .xz(), .mz(), .vz(), .inf(), .xinf(xinfa), .qnan(), .snan(), .nan(nana));
wire [127:0] sq_o;
wire [127:0] sq_o;
fcvtsq u2 (a, sq_o);
//fcvtsq u2 (a[31:0], sq_o);
 
wire [79:0] sdo;
 
fs2d u5 (a[43:4], sdo);
 
wire [39:0] dso;
 
fd2s u6 (a, dso);
 
wire [79:0] f32to80o;
 
wire [31:0] f80to32o;
 
F32ToF80 u7 (a[35:4], f32to80o);
 
F80ToF32 u8 (a[WID+3:4], f32to80o);
 
 
always @*
always @*
    case(op)
  case(op4)
    `FLOAT:
  `FLT1:
        case(fn3)
    case(func5)
        3'b000:
    `FABS:   begin o <= {1'b0,a[WID-2:0]}; nanx <= nanxab; end
            case(fn)
    `FNABS:  begin o <= {1'b1,a[WID-2:0]}; nanx <= nanxab; end
            `FABS:   o <= {1'b0,a[WID-2:0]};        // fabs
    `FNEG:   begin o <= {~a[WID-1],a[WID-2:0]};  nanx <= nanxab; end
            `FNABS:  o <= {1'b1,a[WID-2:0]};        // fnabs
    `FMOV:   begin o <= a; nanx <= nanxab; end
            `FNEG:   o <= {~a[WID-1],a[WID-2:0]};   // fneg
    `FSIGN:  begin o <= (a[WID-2:0]==0) ? 0 : {a[WID-1],1'b0,{EMSB{1'b1}},{FMSB+1{1'b0}}}; nanx <= 1'b0; end
            `FMOV:   o <= a;                        // fmov
    `FMAN:   begin o <= {a[WID-1],1'b0,{EMSB{1'b1}},a[FMSB:0]}; nanx <= 1'b0; end
            `FSIGN:  o <= (a[WID-2:0]==0) ? 0 : {a[WID-1],1'b0,{EMSB{1'b1}},{FMSB+1{1'b0}}};    // fsign
    //`FCVTSQ:    o <= sq_o;
            `FMAN:   o <= {a[WID-1],1'b0,{EMSB{1'b1}},a[FMSB:0]};    // fman
    `FCVTSD: begin o <= {sdo,4'h0}; nanx <= nanxab; end
            `FCVTSQ:    o <= sq_o;
    `FCVTDS: begin o <= {{40{dso[39]}},dso,4'h0}; nanx <= nanxab; end
 
    `F32TO80: begin o <= {f32to80o,4'h0}; nanx <= nanxab; end
 
    `F80TO32: begin o <= {f80to32o,4'h0}; nanx <= nanxab; end
 
    `ISNAN:      begin o <= nana; end
 
    `FINITE:    begin o <= !xinfa; end
 
    `UNORD:             begin o <= nanxab; end
            default: o <= 0;
            default: o <= 0;
            endcase
            endcase
        // FCMP
  `FLT2:
        3'b001:  o <= cmp_o;
    case(func5)
 
    `FCMP:   begin o <= {cmp_o,4'h0}; nanx <= nanxab; end
 
    `FSLT:       begin o <=  {cmp_o[1],4'h0}; nanx <= nanxab; end
 
    `FSGE:       begin o <= {~cmp_o[1],4'h0}; nanx <= nanxab; end
 
    `FSLE:       begin o <=  {cmp_o[2],4'h0}; nanx <= nanxab; end
 
    `FSGT:       begin o <= ~{cmp_o[2],4'h0}; nanx <= nanxab; end
 
    `FSEQ:       begin o <=  {cmp_o[0],4'h0}; nanx <= nanxab; end
 
    `FSNE:       begin o <= ~{cmp_o[0],4'h0}; nanx <= nanxab; end
 
    `FSUN:       begin o <=  {cmp_o[4],4'h0}; nanx <= nanxab; end
 
    `CPYSGN:    begin o <= {b[WID+3],a[WID+2:0]}; end
 
    default: o <= 0;
 
    endcase
 
  `FLT3:
 
        case(func5)
 
          `FMAX:
 
                begin
 
                  o <= ~cmp_o[2] & ~cmpac_o[2] ? a : ~cmpbc_o[2] ? b : c;
 
                                nanx <= nanxab|nanxac|nanxbc;
 
                end
 
          `FMIN:
 
                begin
 
                        o <=  cmp_o[1] & cmpac_o[1] ? a : cmpbc_o[2] ? b : c;
 
                                nanx <= nanxab|nanxac|nanxbc;
 
                end
 
    default: o <= 0;
 
        endcase
 
  `FANDI:
 
        begin
 
        case(ir[32:31])
 
        2'd0:           o <= {a[23: 4] & {{58{1'b1}},ir[39:33],ir[30:16],4'h0}};
 
        2'd1:           o <= a[43:24] & {{36{1'b1}},ir[39:33],ir[30:16],{20{1'b1}}};
 
        2'd2:           o <= a[63:44] & {{14{1'b1}},ir[39:33],ir[30:16],{40{1'b1}}};
 
        2'd3:           o <= a[83:64] & {ir[39:33],ir[30:16],{60{1'b1}}};
 
        endcase
 
        nanx <= 1'b0;
 
        end
 
  `FORI:
 
        begin
 
        case(ir[32:31])
 
        2'd0:           o <= {a[23: 4] & {{58{1'b0}},ir[39:33],ir[30:16],4'h0}};
 
        2'd1:           o <= a[43:24] & {{36{1'b0}},ir[39:33],ir[30:16],{20{1'b0}}};
 
        2'd2:           o <= a[63:44] & {{14{1'b0}},ir[39:33],ir[30:16],{40{1'b0}}};
 
        2'd3:           o <= a[83:64] & {ir[39:33],ir[30:16],{60{1'b0}}};
        endcase
        endcase
 
        nanx <= 1'b0;
 
        end
        default:        o <= 0;
        default:        o <= 0;
        endcase
        endcase
 
 
endmodule
endmodule
 
 
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