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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2016 Robert Finch, Stratford
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// \\__/ o\ (C) 2006-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpdivr2.v
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// Radix 2 floating point divider primitive
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// fpdivr2.v
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// Radix 2 floating point divider primitive
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//
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// ============================================================================
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// ============================================================================
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//
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module fpdivr2
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#( parameter WID = 24 )
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(
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input clk,
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input ld,
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input [WID-1:0] a,
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input [WID-1:0] b,
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output reg [WID*2-1:0] q,
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output [WID-1:0] r,
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output done
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);
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localparam DMSB = WID-1;
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reg [DMSB:0] rx [2:0]; // remainder holds
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reg [DMSB:0] rxx;
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reg [7:0] cnt; // iteration count
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wire [DMSB:0] sdq;
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wire [DMSB:0] sdr;
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wire sdval = 1'b0;
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wire sdbz;
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reg willGo0;
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//specialCaseDivider #(WID) u1 (.a(a), .b(b), .q(sdq), .r(sdr), .val(sdval), .dbz(sdbz) );
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initial begin
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module fpdivr2(clk4x, ld, a, b, q, r, done, lzcnt);
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rx[0] = 0;
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parameter WID = 112;
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parameter RADIX = 2;
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localparam WID1 = WID;//((WID+2)/3)*3; // make width a multiple of three
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localparam DMSB = WID1-1;
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input clk4x;
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input ld;
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input [WID1-1:0] a;
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input [WID1-1:0] b;
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output reg [WID1*2-1:0] q = 0;
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output reg [WID1-1:0] r = 0;
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output reg done = 1'b0;
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output reg [7:0] lzcnt;
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reg [8:0] cnt; // iteration count
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reg [WID1*2-1:0] qi = 0;
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reg [DMSB+1:0] ri = 0;
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wire b0;
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reg gotnz; // got a non-zero bit
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reg done1;
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wire [7:0] maxcnt;
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assign b0 = b <= ri;
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wire [DMSB+1:0] r1 = b0 ? ri - b : ri;
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assign maxcnt = WID1*2;
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// Done pulse for external circuit. Must span over 1 1x clock so that it's
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// recognized.
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always @(posedge clk4x)
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if (ld)
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done <= 1'b0;
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else if (cnt==9'h1FE)
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done <= 1'b1;
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else if (cnt==9'h1F7)
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done <= 1'b0;
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// Internal done pulse
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always @(posedge clk4x)
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begin
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done1 <= 1'b0;
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if (ld)
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done1 <= 1'b0;
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else if (cnt==9'h1FF)
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done1 <= 1'b1;
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end
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end
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always @(posedge clk)
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always @(posedge clk4x)
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if (ld)
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if (ld)
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cnt <= sdval ? 8'b10000000 : WID*2-2;
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cnt <= maxcnt;
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else if (!done)
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else if (cnt != 9'h1F7)
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cnt <= cnt - 1;
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cnt <= cnt - 8'd1;
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always @(posedge clk4x)
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always @(posedge clk)
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if (ld)
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if (ld) begin
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gotnz <= 1'b0;
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rxx <= 0;
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else if (!cnt[8]) begin
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if (sdval)
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if (b0)
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q <= {sdq,{WID{1'b0}}};
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gotnz <= 1'b1;
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else
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q <= {a,{WID{1'b0}}};
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end
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else if (!done) begin
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willGo0 = {rxx ,q[WID*2-1 ]} > b;
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rx[0] = willGo0 ? {rxx ,q[WID*2-1 ]} - b : {rxx ,q[WID*2-1 ]};
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q[WID*2-1:1] <= q[WID*2-1-1:0];
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q[0] <= willGo0;
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rxx <= rx[0];
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end
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end
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// correct remainder
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wire cnt81;
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assign r = sdval ? sdr : rx[2][DMSB] ? rx[2] + b : rx[2];
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delay1 #(1) u1 (clk4x, 1'b1, cnt[8], cnt81);
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assign done = cnt[7];
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endmodule
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/*
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module fpdivr2_tb();
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reg rst;
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always @(posedge clk4x)
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reg clk;
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if (ld)
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reg ld;
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lzcnt <= 8'h00;
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reg [6:0] cnt;
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else if (!cnt81) begin
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if (b0==1'b0 && !gotnz)
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wire ce = 1'b1;
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lzcnt <= lzcnt + 8'd1;
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wire [23:0] a = 24'h0_4000;
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end
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wire [23:0] b = 24'd101;
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wire [45:0] q;
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wire [23:0] r;
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wire done;
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initial begin
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clk = 1;
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rst = 0;
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#100 rst = 1;
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#100 rst = 0;
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end
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always #20 clk = ~clk; // 25 MHz
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always @(posedge clk)
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if (rst)
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cnt <= 0;
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else begin
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ld <= 0;
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cnt <= cnt + 1;
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if (cnt == 3)
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ld <= 1;
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$display("ld=%b q=%h r=%h done=%b", ld, q, r, done);
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end
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always @(posedge clk4x)
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if (ld)
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qi <= {3'b0,a,{WID1{1'b0}}};
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else if (!cnt81)
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qi[WID1*2-1:0] <= {qi[WID1*2-1-1:0],b0};
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fpdivr2 #(24) divu0(.clk(clk), .ld(ld), .a(a), .b(b), .q(q), .r(r), .done(done) );
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always @(posedge clk4x)
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if (ld)
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ri <= 0;
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else if (!cnt81)
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ri <= {r1[DMSB:0],qi[WID1*2-1]};
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always @(posedge clk4x)
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if (done1)
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q <= qi;
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always @(posedge clk4x)
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if (done1)
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r <= ri;
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endmodule
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endmodule
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*/
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No newline at end of file
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No newline at end of file
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