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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2016 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpdivr8.v
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// fpdivr8.v
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// Radix 8 floating point divider primitive
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// Radix8 doesn't work !!!!
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// Radix 2 floating point divider primitive
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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//
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//
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// ============================================================================
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// ============================================================================
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module fpdivr8(clk, ld, a, b, q, r, done, lzcnt);
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module fpdivr8(clk, ld, a, b, q, r, done, lzcnt);
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parameter WID = 112;
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parameter WID = 112;
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parameter RADIX = 8;
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localparam DMSB = WID-1;
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localparam WID1 = WID;//((WID+2)/3)*3; // make width a multiple of three
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localparam DMSB = WID1-1;
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input clk;
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input clk;
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input ld;
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input ld;
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input [WID1-1:0] a;
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input [WID-1:0] a;
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input [WID1-1:0] b;
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input [WID-1:0] b;
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output reg [WID1*2-1:0] q;
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output reg [WID-1:0] q;
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output [WID1-1:0] r;
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output [WID-1:0] r;
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output reg done;
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output reg done;
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output reg [7:0] lzcnt;
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output reg [7:0] lzcnt;
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wire [DMSB:0] rx [2:0]; // remainder holds
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reg [DMSB:0] rxx;
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reg [DMSB:0] rxx;
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reg [8:0] cnt; // iteration count
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reg [8:0] cnt; // iteration count
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wire [DMSB:0] sdq;
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wire [DMSB:0] sdr;
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wire sdval;
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wire sddbz;
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reg [DMSB+1:0] ri = 0;
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reg [DMSB+1:0] ri = 0;
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wire b0,b1,b2;
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wire b0,b1,b2,b3;
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wire [DMSB+1:0] r1,r2,r3;
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wire [DMSB+1:0] r1,r2,r3;
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reg gotnz;
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reg gotnz;
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specialCaseDivider #(WID1) u1 (.a(a), .b(b), .q(sdq), .val(sdval), .dbz(sdbz) );
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wire [7:0] maxcnt;
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wire [7:0] maxcnt;
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wire [2:0] n1;
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wire [2:0] n1;
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generate
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assign maxcnt = WID/3+1;
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begin
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if (RADIX==8) begin
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assign maxcnt = WID1*2/3+1;
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assign b0 = b < rxx;
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assign b0 = b < rxx;
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assign r1 = b0 ? rxx - b : rxx;
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assign r1 = b0 ? rxx - b : rxx;
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assign b1 = b < {r1,q[WID*2-1]};
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assign b1 = b < {r1,q[WID-1]};
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assign r2 = b1 ? {r1,q[WID*2-1]} - b : {r1,q[WID*2-1]};
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assign r2 = b1 ? {r1,q[WID-1]} - b : {r1,q[WID-1]};
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assign b2 = b < {r2,q[WID*2-1-1]};
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assign b2 = b < {r2,q[WID-2]};
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assign r3 = b2 ? {r2,q[WID*2-1-1]} - b : {r2,q[WID*2-1-1]};
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assign r3 = b2 ? {r2,q[WID-2]} - b : {r2,q[WID-2]};
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assign n1 = 2;
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always @(posedge clk)
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always @(posedge clk)
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if (ld)
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if (ld)
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rxx <= 0;
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rxx <= {WID{1'b0}};
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else if (!done)
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else if (!done)
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rxx <= {r3,q[WID*2-1]};
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rxx <= {r3,q[WID-3]};
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end
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else if (RADIX==2) begin
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assign b0 = b <= ri;
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assign r1 = b0 ? ri - b : ri;
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assign maxcnt = WID1*2-1;
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assign n1 = 0;
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// assign rx[0] = rxx [DMSB] ? {rxx ,q[WID*2-1 ]} + b : {rxx ,q[WID*2-1 ]} - b;
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end
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end
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endgenerate
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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done <= 1'b0;
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done <= 1'b0;
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if (ld) begin
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if (ld) begin
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cnt <= sdval ? 9'h1FE : maxcnt;
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cnt <= maxcnt;
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done <= sdval;
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end
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end
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else if (cnt != 9'h1FE) begin
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else if (cnt != 9'h1FE) begin
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cnt <= cnt - 1;
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cnt <= cnt - 1;
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if (cnt==9'h1FF)
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if (cnt==9'h1FF)
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done <= 1'b1;
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done <= 1'b1;
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end
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end
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end
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end
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generate
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begin
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if (RADIX==8) begin
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always @(posedge clk)
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always @(posedge clk)
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if (ld) begin
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if (ld) begin
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gotnz <= 1'b0;
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q <= a;
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lzcnt <= 8'h00;
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if (sdval)
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q <= {3'b0,sdq,{WID1{1'b0}}};
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else
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q <= {3'b0,a,{WID1{1'b0}}};
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end
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end
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else if (!done) begin
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else if (!done) begin
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q[WID1-1:3] <= q[WID1-1-3:0];
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q[WID-1:3] <= q[WID-4:0];
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q[0] <= b0;
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q[2] <= b0;
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q[1] <= b1;
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q[1] <= b1;
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q[2] <= b2;
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q[0] <= b2;
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end
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// correct remainder
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assign r = sdval ? sdr : r3;
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end
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end
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if (RADIX==2) begin
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assign r = r3;
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always @(posedge clk)
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if (ld) begin
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gotnz <= 1'b0;
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lzcnt <= 8'h00;
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ri <= 0;
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if (sdval)
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q <= {3'b0,sdq,{WID1{1'b0}}};
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else
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q <= {3'b0,a,{WID1{1'b0}}};
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end
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else if (cnt!=9'h1FE) begin
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if (b0)
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gotnz <= 1'b1;
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if (b0==0 && !gotnz)
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lzcnt <= lzcnt + 8'd1;
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q[WID1*2-1:1] <= q[WID1*2-1-1:0];
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q[0] <= b0;
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ri <= {r1[DMSB:0],q[WID1*2-1]};
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end
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// correct remainder
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assign r = sdval ? sdr : ri;
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end
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end
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endgenerate
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endmodule
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endmodule
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