| Line 34... |
Line 34... |
input ce,
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input ce,
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input [2:0] rm, // rounding mode
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input [2:0] rm, // rounding mode
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input [WID-1:0] i, // integer input
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input [WID-1:0] i, // integer input
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output [WID-1:0] o // float output
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output [WID-1:0] o // float output
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);
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);
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localparam MSB = WID-1;
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`include "fpSize.sv"
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 35 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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wire [EMSB:0] zeroXp = {EMSB{1'b1}};
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wire [EMSB:0] zeroXp = {EMSB{1'b1}};
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wire iz; // zero input ?
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wire iz; // zero input ?
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wire [MSB:0] imag; // get magnitude of i
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wire [MSB:0] imag; // get magnitude of i
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| Line 76... |
Line 54... |
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(i[MSB]), .o(so) );
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delay1 #(1) u3 (.clk(clk), .ce(ce), .i(i[MSB]), .o(so) );
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generate
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generate
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if (WID==128) begin
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if (WID==128) begin
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cntlz128Reg u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
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cntlz128Reg u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
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end else if (WID==96) begin
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end else if (WID==96) begin
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cntlz96Reg u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
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cntlz96Reg u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
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assign lz[7]=1'b0;
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end else if (WID==84) begin
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cntlz96Reg u4 (.clk(clk), .ce(ce), .i({imag1,12'hfff}), .o(lz[6:0]) );
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assign lz[7]=1'b0;
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end else if (WID==80) begin
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end else if (WID==80) begin
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cntlz80Reg u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
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cntlz80Reg u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
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assign lz[7]=1'b0;
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end else if (WID==64) begin
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end else if (WID==64) begin
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cntlz64Reg u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
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cntlz64Reg u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
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assign lz[7]=1'b0;
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end else begin
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end else begin
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cntlz32Reg u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
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cntlz32Reg u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[5:0]) );
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assign lz[6]=1'b0;
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assign lz[7:6]=2'b00;
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end
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end
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endgenerate
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endgenerate
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assign wd = zeroXp - 1 + WID - lz; // constant except for lz
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assign wd = zeroXp - 1 + WID - lz; // constant except for lz
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| Line 122... |
Line 106... |
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reg clk;
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reg clk;
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reg [7:0] cnt;
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reg [7:0] cnt;
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wire [31:0] fo;
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wire [31:0] fo;
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reg [31:0] i;
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reg [31:0] i;
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wire [79:0] fo80;
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initial begin
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initial begin
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clk = 1'b0;
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clk = 1'b0;
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cnt = 0;
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cnt = 0;
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end
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end
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always #10 clk=!clk;
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always #10 clk=!clk;
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| Line 138... |
Line 123... |
8'd0: i <= 32'd0;
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8'd0: i <= 32'd0;
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8'd1: i <= 32'd16777226;
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8'd1: i <= 32'd16777226;
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endcase
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endcase
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i2f #(32) u1 (.clk(clk), .ce(1), .rm(2'd0), .i(i), .o(fo) );
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i2f #(32) u1 (.clk(clk), .ce(1), .rm(2'd0), .i(i), .o(fo) );
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i2f #(80) u2 (.clk(clk), .ce(1), .rm(2'd0), .i(i), .o(fo) );
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i2f #(80) u2 (.clk(clk), .ce(1), .rm(2'd0), .i({{48{i[31]}},i}), .o(fo80) );
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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