OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog/] [i2f.v] - Diff between revs 8 and 26

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 8 Rev 26
Line 34... Line 34...
        input ce,
        input ce,
        input [2:0] rm,                  // rounding mode
        input [2:0] rm,                  // rounding mode
        input [WID-1:0] i,               // integer input
        input [WID-1:0] i,               // integer input
        output [WID-1:0] o               // float output
        output [WID-1:0] o               // float output
);
);
localparam MSB = WID-1;
`include "fpSize.sv"
localparam EMSB = WID==128 ? 14 :
 
                  WID==96 ? 14 :
 
                  WID==80 ? 14 :
 
                  WID==64 ? 10 :
 
                                  WID==52 ? 10 :
 
                                  WID==48 ? 10 :
 
                                  WID==44 ? 10 :
 
                                  WID==42 ? 10 :
 
                                  WID==40 ?  9 :
 
                                  WID==32 ?  7 :
 
                                  WID==24 ?  6 : 4;
 
localparam FMSB = WID==128 ? 111 :
 
                  WID==96 ? 79 :
 
                  WID==80 ? 63 :
 
                  WID==64 ? 51 :
 
                                  WID==52 ? 39 :
 
                                  WID==48 ? 35 :
 
                                  WID==44 ? 31 :
 
                                  WID==42 ? 29 :
 
                                  WID==40 ? 28 :
 
                                  WID==32 ? 22 :
 
                                  WID==24 ? 15 : 9;
 
 
 
wire [EMSB:0] zeroXp = {EMSB{1'b1}};
wire [EMSB:0] zeroXp = {EMSB{1'b1}};
 
 
wire iz;                        // zero input ?
wire iz;                        // zero input ?
wire [MSB:0] imag;       // get magnitude of i
wire [MSB:0] imag;       // get magnitude of i
Line 76... Line 54...
delay1 #(1)   u3 (.clk(clk), .ce(ce), .i(i[MSB]), .o(so) );
delay1 #(1)   u3 (.clk(clk), .ce(ce), .i(i[MSB]), .o(so) );
generate
generate
if (WID==128) begin
if (WID==128) begin
cntlz128Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
cntlz128Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
end else if (WID==96) begin
end else if (WID==96) begin
cntlz96Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
cntlz96Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
 
assign lz[7]=1'b0;
 
end else if (WID==84) begin
 
cntlz96Reg    u4 (.clk(clk), .ce(ce), .i({imag1,12'hfff}), .o(lz[6:0]) );
 
assign lz[7]=1'b0;
end else if (WID==80) begin
end else if (WID==80) begin
cntlz80Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
cntlz80Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
 
assign lz[7]=1'b0;
end else if (WID==64) begin
end else if (WID==64) begin
cntlz64Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
cntlz64Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
 
assign lz[7]=1'b0;
end else begin
end else begin
cntlz32Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
cntlz32Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[5:0]) );
assign lz[6]=1'b0;
assign lz[7:6]=2'b00;
end
end
endgenerate
endgenerate
 
 
assign wd = zeroXp - 1 + WID - lz;      // constant except for lz
assign wd = zeroXp - 1 + WID - lz;      // constant except for lz
 
 
Line 122... Line 106...
 
 
reg clk;
reg clk;
reg [7:0] cnt;
reg [7:0] cnt;
wire [31:0] fo;
wire [31:0] fo;
reg [31:0] i;
reg [31:0] i;
 
wire [79:0] fo80;
initial begin
initial begin
clk = 1'b0;
clk = 1'b0;
cnt = 0;
cnt = 0;
end
end
always #10 clk=!clk;
always #10 clk=!clk;
Line 138... Line 123...
8'd0:   i <= 32'd0;
8'd0:   i <= 32'd0;
8'd1:   i <= 32'd16777226;
8'd1:   i <= 32'd16777226;
endcase
endcase
 
 
i2f #(32) u1 (.clk(clk), .ce(1), .rm(2'd0), .i(i), .o(fo) );
i2f #(32) u1 (.clk(clk), .ce(1), .rm(2'd0), .i(i), .o(fo) );
i2f #(80) u2 (.clk(clk), .ce(1), .rm(2'd0), .i(i), .o(fo) );
i2f #(80) u2 (.clk(clk), .ce(1), .rm(2'd0), .i({{48{i[31]}},i}), .o(fo80) );
 
 
endmodule
endmodule
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.