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https://opencores.org/ocsvn/ft816float/ft816float/trunk
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Rev 70 |
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Line 124... |
BCDAddAdjust u1 (hsN[g],o[g*4+3:g*4],c[g+1]);
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BCDAddAdjust u1 (hsN[g],o[g*4+3:g*4],c[g+1]);
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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/*
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module BCDAdd8NClk(clk, a, b, o, ci, co);
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parameter N=33;
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input clk;
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input [N*8-1:0] a;
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input [N*8-1:0] b;
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output [N*8-1:0] o;
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input ci;
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output co;
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reg [N:0] c;
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wire [N:0] d;
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assign c[0] = ci;
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assign co = c[N];
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genvar g;
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generate begin : gBCDadd
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for (g = 0; g < N; g = g + 1) begin
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BCDAdd u1 (c[g],a[g*8+7:g*8],b[g*8+7:g*8],o[g*8+7:g*8],d[g+1]);
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always_ff @(posedge clk)
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c[g+1] <= d[g+1];
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end
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end
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endgenerate
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endmodule
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*/
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module BCDSub(ci,a,b,o,c);
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module BCDSub(ci,a,b,o,c);
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input ci; // carry input
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input ci; // carry input
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input [7:0] a;
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input [7:0] a;
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input [7:0] b;
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input [7:0] b;
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Line 192... |
end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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/*
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module BCDSub8NClk(clk, a, b, o, ci, co);
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parameter N=33;
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input clk;
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input [N*8-1:0] a;
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input [N*8-1:0] b;
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output [N*8-1:0] o;
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input ci;
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output co;
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reg [N:0] c;
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wire [N:0] d;
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assign c[0] = ci;
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assign co = c[N];
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genvar g;
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generate begin : gBCDsub
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for (g = 0; g < N; g = g + 1) begin
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BCDSub u1 (c[g],a[g*8+7:g*8],b[g*8+7:g*8],o[g*8+7:g*8],d[g+1]);
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always_ff @(posedge clk)
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c[g+1] <= d[g+1];
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end
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end
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endgenerate
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endmodule
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*/
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module BCDAddAdjust(i,o,c);
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module BCDAddAdjust(i,o,c);
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input [4:0] i;
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input [4:0] i;
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output [3:0] o;
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output [3:0] o;
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reg [3:0] o;
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reg [3:0] o;
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