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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [BCDMath.sv] - Diff between revs 70 and 80

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Rev 70 Rev 80
Line 98... Line 98...
BCDAddAdjust u3 (hsN2,o[11:8],c2);
BCDAddAdjust u3 (hsN2,o[11:8],c2);
BCDAddAdjust u4 (hsN3,o[15:12],c);
BCDAddAdjust u4 (hsN3,o[15:12],c);
 
 
endmodule
endmodule
 
 
module BCDAddN(ci,a,b,o,co);
module BCDAddNClk(clk,ci,a,b,o,co);
parameter N=24;
parameter N=25;
input ci;               // carry input
input clk;
 
input ci;
input [N*4-1:0] a;
input [N*4-1:0] a;
input [N*4-1:0] b;
input [N*4-1:0] b;
output [N*4-1:0] o;
output reg [N*4-1:0] o;
output co;
output reg co;
 
 
genvar g;
 
generate begin : gBCDAddN
 
reg [4:0] hsN [0:N-1];
 
wire [N:0] c;
 
 
 
assign c[0] = ci;
 
assign co = c[N];
 
 
 
for (g = 0; g < N; g = g + 1)
reg [N-1:0] cg;
        always @*
wire [N*4-1:0] s;
                hsN[g] = a[g*4+3:g*4] + b[g*4+3:g*4] + c[g];
reg [N*4-1:0] on [0:3];
 
reg [3:0] cn;
 
 
 
genvar g;
 
generate begin :gAdd
for (g = 0; g < N; g = g + 1)
for (g = 0; g < N; g = g + 1)
        BCDAddAdjust u1 (hsN[g],o[g*4+3:g*4],c[g+1]);
        BCDAddNyb u1 (
 
                .ci(g==0 ? ci : cg[g-1]),
 
                .a(a[g*4+3:g*4]),
 
                .b(b[g*4+3:g*4]),
 
                .o(s[g*4+3:g*4]),
 
                .c(cg[g])
 
        );
end
end
endgenerate
endgenerate
 
 
endmodule
always_ff @(posedge clk)
 
        on[0] <= s;
module BCDSub(ci,a,b,o,c);
always_ff @(posedge clk)
input ci;               // carry input
        on[1] <= on[0];
input [7:0] a;
always_ff @(posedge clk)
input [7:0] b;
        on[2] <= on[1];
output [7:0] o;
always_ff @(posedge clk)
output c;
        o <= on[2];
 
always_ff @(posedge clk)
wire c0,c1;
        cn[0] <= cg[N-1];
 
always_ff @(posedge clk)
wire [4:0] hdN0 = a[3:0] - b[3:0] - ci;
        cn[1] <= cn[0];
wire [4:0] hdN1 = a[7:4] - b[7:4] - c0;
always_ff @(posedge clk)
 
        cn[2] <= cn[1];
BCDSubAdjust u1 (hdN0,o[3:0],c0);
always_ff @(posedge clk)
BCDSubAdjust u2 (hdN1,o[7:4],c);
        co <= cn[2];
 
 
endmodule
endmodule
 
 
module BCDSub4(ci,a,b,o,c,c8);
module BCDAddN(ci,a,b,o,co);
input ci;               // carry input
parameter N=25;
input [15:0] a;
input ci;
input [15:0] b;
input [N*4-1:0] a;
output [15:0] o;
input [N*4-1:0] b;
output c;
output [N*4-1:0] o;
output c8;
output co;
 
 
 
reg [N-1:0] cg;
 
wire [N*4-1:0] s;
 
 
wire c0,c1,c2;
genvar g;
assign c8 = c1;
generate begin :gAdd
 
        for (g = 0; g < N; g = g + 1)
 
        BCDAddNyb u1 (
 
                .ci(g==0 ? ci : cg[g-1]),
 
                .a(a[g*4+3:g*4]),
 
                .b(b[g*4+3:g*4]),
 
                .o(s[g*4+3:g*4]),
 
                .c(cg[g])
 
        );
 
end
 
endgenerate
 
 
wire [4:0] hdN0 = a[3:0] - b[3:0] - ci;
assign o = s;
wire [4:0] hdN1 = a[7:4] - b[7:4] - c0;
assign co = cg[N-1];
wire [4:0] hdN2 = a[11:8] - b[11:8] - c1;
 
wire [4:0] hdN3 = a[15:12] - b[15:12] - c2;
 
 
 
BCDSubAdjust u1 (hdN0,o[3:0],c0);
 
BCDSubAdjust u2 (hdN1,o[7:4],c1);
 
BCDSubAdjust u3 (hdN2,o[11:8],c2);
 
BCDSubAdjust u4 (hdN3,o[15:12],c);
 
 
 
endmodule
endmodule
 
 
module BCDSubN(ci,a,b,o,co);
/*
 
module BCDAddN(ci,a,b,o,co);
parameter N=24;
parameter N=24;
input ci;               // carry input
input ci;               // carry input
input [N*4-1:0] a;
input [N*4-1:0] a;
input [N*4-1:0] b;
input [N*4-1:0] b;
output [N*4-1:0] o;
output [N*4-1:0] o;
output co;
output co;
 
 
genvar g;
genvar g;
generate begin : gBCDSubN
generate begin : gBCDAddN
reg [4:0] hdN [0:N-1];
reg [4:0] hsN [0:N-1];
wire [N:0] c;
wire [N:0] c;
 
 
assign c[0] = ci;
assign c[0] = ci;
assign co = c[N];
assign co = c[N];
 
 
for (g = 0; g < N; g = g + 1)
for (g = 0; g < N; g = g + 1)
        always @*
        always @*
                hdN[g] = a[g*4+3:g*4] - b[g*4+3:g*4] - c[g];
                hsN[g] = a[g*4+3:g*4] + b[g*4+3:g*4] + c[g];
 
 
for (g = 0; g < N; g = g + 1)
for (g = 0; g < N; g = g + 1)
        BCDSubAdjust u1 (hdN[g],o[g*4+3:g*4],c[g+1]);
        BCDAddAdjust u1 (hsN[g],o[g*4+3:g*4],c[g+1]);
end
end
endgenerate
endgenerate
 
 
endmodule
endmodule
 
*/
 
 
module BCDAddAdjust(i,o,c);
module BCDAddAdjust(i,o,c);
input [4:0] i;
input [4:0] i;
output [3:0] o;
output [3:0] o;
reg [3:0] o;
reg [3:0] o;
output c;
output c;

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