URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [BCDMath.v] - Diff between revs 53 and 54

Rev 53	Rev 54
Line 34...	Line 34...
`// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE`	`// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE`
`// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`	`// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
`//`	`//`
`// ============================================================================`	`// ============================================================================`
`//`	`//`
	`// Could use the following approach for add/sub but it ends up being larger`
	`// than using an adjustment lookup table.`

	`module BCDAddNyb(ci,a,b,o,c);`
	`input ci; // carry input`
	`input [3:0] a;`
	`input [3:0] b;`
	`output [3:0] o;`
	`output c;`

	`wire c0;`

	`reg [4:0] hsN0;`
	`always @*`
	`begin`
	`hsN0 = a[3:0] + b[3:0] + ci;`
	`if (hsN0 > 5'd9)`
	`hsN0 = hsN0 + 3'd6;`
	`end`
	`assign o = hsN0[3:0];`
	`assign c = hsN0[4];`

	`endmodule`

`module BCDAdd(ci,a,b,o,c);`	`module BCDAdd(ci,a,b,o,c);`
`input ci; // carry input`	`input ci; // carry input`
`input [7:0] a;`	`input [7:0] a;`
`input [7:0] b;`	`input [7:0] b;`
`output [7:0] o;`	`output [7:0] o;`