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https://opencores.org/ocsvn/ft816float/ft816float/trunk
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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// Perform a logical shift to the right.
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module BCDSRL(ci, i, o, co);
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parameter N=4;
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input ci;
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input [N*4-1:0] i;
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output reg [N*4-1:0] o;
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output co;
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reg [N:0] c;
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genvar g;
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generate begin
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always @*
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c[N] = ci;
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for (g = N - 1; g >= 0; g = g - 1)
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always @*
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c[g] = i[g*4];
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for (g = N - 1; g >= 0; g = g - 1)
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always @*
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begin
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o[g*4+3:g*4] = {1'b0,i[g*4+3:g*4+1]};
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// Because there is a divide by two, the value will range between 0 and 4.
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// Adding 5 keeps it within deicmal boundaries of 0 to 9. No carry can be
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// generated
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if (c[N+1])
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o[g*4+3:g*4] = o[g*4+3:g*4] + 4'd5;
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end
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assign co = c[0];
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end
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endgenerate
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endmodule
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