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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [BCDSub8NClk.sv] - Diff between revs 66 and 70

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Line 59... Line 59...
//  188888889           <- first row result
//  188888889           <- first row result
// + 11111110           <- carries out of first row
// + 11111110           <- carries out of first row
//---------------
//---------------
//  199999999   <- second row result
//  199999999   <- second row result
 
 
module BCDSub8NClk(clk, ld, a, b, o, ci, co, done);
module BCDSub8NClk(clk, a, b, o, ci, co);
parameter N=33;
parameter N=33;
input clk;
input clk;
input ld;
 
input [N*8-1:0] a;
input [N*8-1:0] a;
input [N*8-1:0] b;
input [N*8-1:0] b;
output reg [N*8-1:0] o;
output reg [N*8-1:0] o;
input ci;
input ci;
output reg co;
output reg co;
output reg done;
 
 
 
reg [N-1:0] c [0:2];
reg [N-1:0] c [0:2];
wire [N*8-1:0] o1 [0:2];
wire [N*8-1:0] o1 [0:2];
reg [N*8-1:0] o2 [0:2];
reg [N*8-1:0] o2 [0:2];
wire [N:0] d [0:2];
wire [N:0] d [0:2];
 
 
genvar g,k;
genvar g,k;
generate begin : gBCDadd
generate begin : gBCDadd
for (g = 0; g < N; g = g + 1) begin
for (g = 0; g < N; g = g + 1) begin
        for (k = 0; k < 3; k = k + 1) begin
        for (k = 0; k < 3; k = k + 1) begin
 
                initial begin
 
                        c[k][g] <= 'b0;
 
                end
                BCDSub u1 (
                BCDSub u1 (
                        .ci(k==0 && g==0 ? ci : 1'b0),
                        .ci(k==0 && g==0 ? ci : 1'b0),
                        .a(k==0 ? a[g*8+7:g*8] : o2[k-1][g*8+7:g*8]),
                        .a(k==0 ? a[g*8+7:g*8] : o2[k-1][g*8+7:g*8]),
                        .b(k==0 ? b[g*8+7:g*8] : {7'h00,c[k-1][g]}),
                        .b(k==0 ? b[g*8+7:g*8] : {7'h00,c[k-1][g]}),
                        .o(o1[k][g*8+7:g*8]),
                        .o(o1[k][g*8+7:g*8]),
Line 95... Line 96...
        end
        end
end
end
always_ff @(posedge clk)
always_ff @(posedge clk)
begin
begin
        o <= o1[2];
        o <= o1[2];
        co <= c[2][N-1];
        co <= c[2][N-1]|c[1][N-1]|c[0][N-1];
end
end
end
end
endgenerate
endgenerate
endmodule
endmodule
 
 

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