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https://opencores.org/ocsvn/ft816float/ft816float/trunk
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Rev 70 |
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Line 59... |
// 188888889 <- first row result
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// 188888889 <- first row result
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// + 11111110 <- carries out of first row
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// + 11111110 <- carries out of first row
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//---------------
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//---------------
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// 199999999 <- second row result
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// 199999999 <- second row result
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module BCDSub8NClk(clk, ld, a, b, o, ci, co, done);
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module BCDSub8NClk(clk, a, b, o, ci, co);
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parameter N=33;
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parameter N=33;
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input clk;
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input clk;
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input ld;
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input [N*8-1:0] a;
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input [N*8-1:0] a;
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input [N*8-1:0] b;
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input [N*8-1:0] b;
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output reg [N*8-1:0] o;
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output reg [N*8-1:0] o;
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input ci;
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input ci;
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output reg co;
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output reg co;
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output reg done;
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reg [N-1:0] c [0:2];
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reg [N-1:0] c [0:2];
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wire [N*8-1:0] o1 [0:2];
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wire [N*8-1:0] o1 [0:2];
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reg [N*8-1:0] o2 [0:2];
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reg [N*8-1:0] o2 [0:2];
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wire [N:0] d [0:2];
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wire [N:0] d [0:2];
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genvar g,k;
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genvar g,k;
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generate begin : gBCDadd
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generate begin : gBCDadd
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for (g = 0; g < N; g = g + 1) begin
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for (g = 0; g < N; g = g + 1) begin
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for (k = 0; k < 3; k = k + 1) begin
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for (k = 0; k < 3; k = k + 1) begin
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initial begin
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c[k][g] <= 'b0;
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end
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BCDSub u1 (
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BCDSub u1 (
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.ci(k==0 && g==0 ? ci : 1'b0),
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.ci(k==0 && g==0 ? ci : 1'b0),
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.a(k==0 ? a[g*8+7:g*8] : o2[k-1][g*8+7:g*8]),
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.a(k==0 ? a[g*8+7:g*8] : o2[k-1][g*8+7:g*8]),
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.b(k==0 ? b[g*8+7:g*8] : {7'h00,c[k-1][g]}),
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.b(k==0 ? b[g*8+7:g*8] : {7'h00,c[k-1][g]}),
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.o(o1[k][g*8+7:g*8]),
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.o(o1[k][g*8+7:g*8]),
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end
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end
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end
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end
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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begin
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begin
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o <= o1[2];
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o <= o1[2];
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co <= c[2][N-1];
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co <= c[2][N-1]|c[1][N-1]|c[0][N-1];
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end
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end
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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