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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [BCDSubtract.sv] - Diff between revs 80 and 83

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Rev 80 Rev 83
Line 43... Line 43...
input [N*4-1:0] a;
input [N*4-1:0] a;
input [N*4-1:0] b;
input [N*4-1:0] b;
output reg [N*4-1:0] o;
output reg [N*4-1:0] o;
output reg sgn;
output reg sgn;
 
 
wire [(N+1)*4-1:0] bc;
wire [(N)*4-1:0] bc;
wire [(N+1)*4-1:0] o1, o2, o3;
wire [(N)*4-1:0] o1, o2, o3;
wire c;
wire c;
 
 
BCDNinesComplementN #(N+1) u1 (.i({4'h0,b}), .o(bc));
BCDNinesComplementN #(N) u1 (.i({4'h0,b}), .o(bc));
BCDAddNClk #(.N(N+1)) u2 (.clk(clk), .a({8'h00,a}), .b(bc), .o(o1), .ci(1'b0), .co(c));
BCDAddNClk #(.N(N)) u2 (.clk(clk), .a({8'h00,a}), .b(bc), .o(o1), .ci(1'b0), .co(c));
BCDNinesComplementN #(N) u3 (.i(o1), .o(o2));
BCDNinesComplementN #(N) u3 (.i(o1), .o(o2));
BCDAddNClk #(.N(N+1)) u4 (.clk(clk), .a(o1), .b('d0), .o(o3), .ci(c), .co());
BCDAddNClk #(.N(N)) u4 (.clk(clk), .a(o1), .b('d0), .o(o3), .ci(c), .co());
 
 
always_ff @(posedge clk)
always_ff @(posedge clk)
        if (c)
        if (c)
                o <= o3;
                o <= o3;
        else
        else
                o <= o2;
                o <= o2;
always_ff @(posedge clk)
always_ff @(posedge clk)
        sgn <= ~c;
        sgn <= |o ? ~c : 1'b0;
 
 
endmodule
endmodule
 
 
module BCDNinesComplement(i, o);
module BCDNinesComplement(i, o);
input [3:0] i;
input [3:0] i;

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