| Line 40... |
Line 40... |
input ce;
|
input ce;
|
input [2:0] rm;
|
input [2:0] rm;
|
input op;
|
input op;
|
input [127:0] a;
|
input [127:0] a;
|
input [127:0] b;
|
input [127:0] b;
|
output [219:0] o;
|
output [243:0] o;
|
|
|
parameter TRUE = 1'b1;
|
parameter TRUE = 1'b1;
|
parameter FALSE = 1'b0;
|
parameter FALSE = 1'b0;
|
|
|
wire sa, sb;
|
wire sa, sb;
|
| Line 52... |
Line 52... |
wire adn, bdn;
|
wire adn, bdn;
|
wire xainf, xbinf;
|
wire xainf, xbinf;
|
wire ainf, binf;
|
wire ainf, binf;
|
wire aNan, bNan;
|
wire aNan, bNan;
|
wire [15:0] xa, xb;
|
wire [15:0] xa, xb;
|
wire [95:0] siga, sigb;
|
wire [107:0] siga, sigb;
|
|
|
wire [15:0] xabdif4;
|
wire [15:0] xabdif4;
|
BCDSub4 ubcds1(
|
BCDSub4 ubcds1(
|
.ci(1'b0),
|
.ci(1'b0),
|
.a(xa_gt_xb4 ? xa4 : xb4),
|
.a(xa_gt_xb4 ? xa4 : xb4),
|
| Line 64... |
Line 64... |
.o(xabdif4),
|
.o(xabdif4),
|
.c(),
|
.c(),
|
.c8()
|
.c8()
|
);
|
);
|
|
|
wire [99:0] oss10;
|
wire [111:0] oss10;
|
wire oss10c;
|
wire oss10c;
|
|
|
BCDAddN #(.N(25)) ubcdan1
|
BCDAddN #(.N(28)) ubcdan1
|
(
|
(
|
.ci(1'b0),
|
.ci(1'b0),
|
.a(oaa10),
|
.a(oaa10),
|
.b(obb10),
|
.b(obb10),
|
.o(oss10),
|
.o(oss10),
|
.co(oss10c)
|
.co(oss10c)
|
);
|
);
|
|
|
wire [99:0] odd10;
|
wire [111:0] odd10;
|
wire odd10c;
|
wire odd10c;
|
|
|
BCDSubN #(.N(25)) ubcdsn1
|
BCDSubN #(.N(28)) ubcdsn1
|
(
|
(
|
.ci(1'b0),
|
.ci(1'b0),
|
.a(oaa10),
|
.a(oaa10),
|
.b(obb10),
|
.b(obb10),
|
.o(odd10),
|
.o(odd10),
|
| Line 120... |
Line 120... |
reg realOp2;
|
reg realOp2;
|
reg op2;
|
reg op2;
|
reg [15:0] xa2, xb2;
|
reg [15:0] xa2, xb2;
|
reg az2, bz2;
|
reg az2, bz2;
|
reg xa_gt_xb2;
|
reg xa_gt_xb2;
|
reg [95:0] siga2, sigb2;
|
reg [107:0] siga2, sigb2;
|
reg sigeq, siga_gt_sigb;
|
reg sigeq, siga_gt_sigb;
|
reg xa_gt_xb2;
|
reg xa_gt_xb2;
|
reg expeq;
|
reg expeq;
|
reg sxo2;
|
reg sxo2;
|
|
|
| Line 176... |
Line 176... |
reg xa_gt_xb3;
|
reg xa_gt_xb3;
|
reg a_gt_b3;
|
reg a_gt_b3;
|
reg op3;
|
reg op3;
|
wire sa3, sb3;
|
wire sa3, sb3;
|
wire [2:0] rm3;
|
wire [2:0] rm3;
|
reg [95:0] mfs3;
|
reg [107:0] mfs3;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) resZero3 <= (realOp2 & expeq & sigeq) || // subtract, same magnitude
|
if (ce) resZero3 <= (realOp2 & expeq & sigeq) || // subtract, same magnitude
|
(az2 & bz2); // both a,b zero
|
(az2 & bz2); // both a,b zero
|
always @(posedge clk)
|
always @(posedge clk)
|
| Line 264... |
Line 264... |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
|
// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
|
// less) then all of the bits will be shifted out to zero. There is no need to
|
// less) then all of the bits will be shifted out to zero. There is no need to
|
// keep track of a difference more than 24.
|
// keep track of a difference more than 24.
|
reg [11:0] xdif6;
|
reg [11:0] xdif6;
|
wire [95:0] mfs6;
|
wire [107:0] mfs6;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) xdif6 <= xdiff5 > 16'h0024 ? 8'h24 : xdiff5[7:0];
|
if (ce) xdif6 <= xdiff5 > 16'h0024 ? 8'h24 : xdiff5[7:0];
|
delay #(.WID(96), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
|
delay #(.WID(108), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #7
|
// Clock #7
|
//
|
//
|
// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
|
// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
|
| Line 279... |
Line 279... |
// reduce the number of regs required.
|
// reduce the number of regs required.
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg sticky6;
|
reg sticky6;
|
wire sticky7;
|
wire sticky7;
|
wire [7:0] xdif7;
|
wire [7:0] xdif7;
|
wire [95:0] mfs7;
|
wire [107:0] mfs7;
|
wire [7:0] xdif6a = {xdif6[7:4] * 10 + xdif6[3:0],2'b00}; // Convert base then *4
|
wire [7:0] xdif6a = {xdif6[7:4] * 10 + xdif6[3:0],2'b00}; // Convert base then *4
|
integer n;
|
integer n;
|
always @* begin
|
always @* begin
|
sticky6 = 1'b0;
|
sticky6 = 1'b0;
|
for (n = 0; n < 96; n = n + 4)
|
for (n = 0; n < 96; n = n + 4)
|
| Line 292... |
Line 292... |
end
|
end
|
|
|
// register inputs to shifter and shift
|
// register inputs to shifter and shift
|
delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) );
|
delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) );
|
delay1 #(8) d15(.clk(clk), .ce(ce), .i(xdif6a), .o(xdif7) );
|
delay1 #(8) d15(.clk(clk), .ce(ce), .i(xdif6a), .o(xdif7) );
|
delay1 #(96) d14(.clk(clk), .ce(ce), .i(mfs6), .o(mfs7) );
|
delay1 #(108) d14(.clk(clk), .ce(ce), .i(mfs6), .o(mfs7) );
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #8
|
// Clock #8
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [99:0] md8;
|
reg [111:0] md8;
|
wire [95:0] siga8, sigb8;
|
wire [107:0] siga8, sigb8;
|
wire xa_gt_xb8;
|
wire xa_gt_xb8;
|
wire a_gt_b8;
|
wire a_gt_b8;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
|
if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
|
|
|
// sync control signals
|
// sync control signals
|
delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
|
delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
|
delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
|
delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
|
delay #(.WID(96), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
|
delay #(.WID(108), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
|
delay #(.WID(96), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
|
delay #(.WID(108), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
|
delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
|
delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #9
|
// Clock #9
|
// Sort operands and perform add/subtract
|
// Sort operands and perform add/subtract
|
// addition can generate an extra bit, subtract can't go negative
|
// addition can generate an extra bit, subtract can't go negative
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [99:0] oa9, ob9;
|
reg [111:0] oa9, ob9;
|
reg a_gt_b9;
|
reg a_gt_b9;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
|
if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
|
if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
|
| Line 328... |
Line 328... |
if (ce) a_gt_b9 <= a_gt_b8;
|
if (ce) a_gt_b9 <= a_gt_b8;
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #10
|
// Clock #10
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [99:0] oaa10;
|
reg [111:0] oaa10;
|
reg [99:0] obb10;
|
reg [111:0] obb10;
|
wire realOp10;
|
wire realOp10;
|
reg [15:0] xo10;
|
reg [15:0] xo10;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
|
if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
|
| Line 343... |
Line 343... |
delay #(.WID(16), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
|
delay #(.WID(16), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #11
|
// Clock #11
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [99:0] mab11;
|
reg [111:0] mab11;
|
reg mab11c;
|
reg mab11c;
|
wire [95:0] siga11, sigb11;
|
wire [107:0] siga11, sigb11;
|
wire abInf11;
|
wire abInf11;
|
wire aNan11, bNan11;
|
wire aNan11, bNan11;
|
reg xoinf11;
|
reg xoinf11;
|
wire op11;
|
wire op11;
|
|
|
| Line 360... |
Line 360... |
|
|
delay #(.WID(1), .DEP(8)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
|
delay #(.WID(1), .DEP(8)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
|
delay #(.WID(1), .DEP(10)) udly11c (.clk(clk), .ce(ce), .i(aNan), .o(aNan11));
|
delay #(.WID(1), .DEP(10)) udly11c (.clk(clk), .ce(ce), .i(aNan), .o(aNan11));
|
delay #(.WID(1), .DEP(10)) udly11d (.clk(clk), .ce(ce), .i(bNan), .o(bNan11));
|
delay #(.WID(1), .DEP(10)) udly11d (.clk(clk), .ce(ce), .i(bNan), .o(bNan11));
|
delay #(.WID(1), .DEP(3)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
|
delay #(.WID(1), .DEP(3)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
|
delay #(.WID(96), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
|
delay #(.WID(108), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
|
delay #(.WID(96), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
|
delay #(.WID(108), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) xoinf11 <= xo10==16'h9999;
|
if (ce) xoinf11 <= xo10==16'h9999;
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #12
|
// Clock #12
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [199:0] mo12; // mantissa output
|
reg [223:0] mo12; // mantissa output
|
reg [3:0] st12;
|
reg [3:0] st12;
|
wire sxo11;
|
wire sxo11;
|
wire so11;
|
wire so11;
|
delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
|
delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
|
delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
|
delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
|
| Line 389... |
Line 389... |
always @(posedge clk)
|
always @(posedge clk)
|
if (ce)
|
if (ce)
|
casez({abInf11,aNan11,bNan11,xoinf11})
|
casez({abInf11,aNan11,bNan11,xoinf11})
|
4'b1???: // inf +/- inf - generate QNaN on subtract, inf on add
|
4'b1???: // inf +/- inf - generate QNaN on subtract, inf on add
|
if (op11)
|
if (op11)
|
mo12 <= {4'h9,196'd0};
|
mo12 <= {4'h9,220'd0};
|
else
|
else
|
mo12 <= {50{4'h9}};
|
mo12 <= {56{4'h9}};
|
4'b01??: mo12 <= {4'b0,siga11[95:0],100'd0};
|
4'b01??: mo12 <= {4'b0,siga11[107:0],112'd0};
|
4'b001?: mo12 <= {4'b0,sigb11[95:0],100'd0};
|
4'b001?: mo12 <= {4'b0,sigb11[107:0],112'd0};
|
4'b0001: mo12 <= 200'd0;
|
4'b0001: mo12 <= 224'd0;
|
default: mo12 <= {3'b0,mab11c,mab11,96'd0}; // mab has an extra lead bit and four trailing bits
|
default: mo12 <= {3'b0,mab11c,mab11,108'd0}; // mab has an extra lead bit and four trailing bits
|
endcase
|
endcase
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #13
|
// Clock #13
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
wire so; // sign output
|
wire so; // sign output
|
wire [3:0] st;
|
wire [3:0] st;
|
wire [15:0] xo; // de normalized exponent output
|
wire [15:0] xo; // de normalized exponent output
|
wire [199:0] mo; // mantissa output
|
wire [223:0] mo; // mantissa output
|
|
|
delay #(.WID(4), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(st12), .o(st[3:0]) );
|
delay #(.WID(4), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(st12), .o(st[3:0]) );
|
delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(so));
|
delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(so));
|
delay #(.WID(16), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(xo));
|
delay #(.WID(16), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(xo));
|
delay #(.WID(200), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(mo12), .o(mo) );
|
delay #(.WID(224), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(mo12), .o(mo) );
|
|
|
assign o = {st,xo,mo};
|
assign o = {st,xo,mo};
|
|
|
endmodule
|
endmodule
|
|
|
| Line 425... |
Line 425... |
input op; // operation 0 = add, 1 = subtract
|
input op; // operation 0 = add, 1 = subtract
|
input [127:0] a; // operand a
|
input [127:0] a; // operand a
|
input [127:0] b; // operand b
|
input [127:0] b; // operand b
|
output [127:0] o; // output
|
output [127:0] o; // output
|
|
|
wire [219:0] o1;
|
wire [243:0] o1;
|
wire [119:0] fpn0;
|
wire [131:0] fpn0;
|
|
|
DFPAddsub u1 (clk, ce, rm, op, a, b, o1);
|
DFPAddsub u1 (clk, ce, rm, op, a, b, o1);
|
DFPNormalize u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
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DFPNormalize u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
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DFPRound u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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DFPRound u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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