| Line 34... |
Line 34... |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
//
|
//
|
// ============================================================================
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// ============================================================================
|
|
|
module DFPAddsub(clk, ce, rm, op, a, b, o);
|
module DFPAddsub(clk, ce, rm, op, a, b, o);
|
|
parameter N=33;
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input clk;
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input clk;
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input ce;
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input ce;
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input [2:0] rm;
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input [2:0] rm;
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input op;
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input op;
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input [127:0] a;
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input [N*4+16+4-1:0] a;
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input [127:0] b;
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input [N*4+16+4-1:0] b;
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output [243:0] o;
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output [(N+1)*4*2+16+4-1:0] o;
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|
|
parameter TRUE = 1'b1;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter FALSE = 1'b0;
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|
|
wire sa, sb;
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wire sa, sb;
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| Line 52... |
Line 53... |
wire adn, bdn;
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wire adn, bdn;
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wire xainf, xbinf;
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wire xainf, xbinf;
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wire ainf, binf;
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wire ainf, binf;
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wire aNan, bNan;
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wire aNan, bNan;
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wire [15:0] xa, xb;
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wire [15:0] xa, xb;
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wire [107:0] siga, sigb;
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wire [N*4-1:0] siga, sigb;
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|
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wire [15:0] xabdif4;
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wire [15:0] xabdif4;
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BCDSub4 ubcds1(
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BCDSub4 ubcds1(
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.ci(1'b0),
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.ci(1'b0),
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.a(xa_gt_xb4 ? xa4 : xb4),
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.a(xa_gt_xb4 ? xa4 : xb4),
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| Line 64... |
Line 65... |
.o(xabdif4),
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.o(xabdif4),
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.c(),
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.c(),
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.c8()
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.c8()
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);
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);
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|
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wire [111:0] oss10;
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wire [(N+1)*4-1:0] oss10;
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wire oss10c;
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wire oss10c;
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|
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BCDAddN #(.N(28)) ubcdan1
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BCDAddN #(.N(N+1)) ubcdan1
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(
|
(
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.ci(1'b0),
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.ci(1'b0),
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.a(oaa10),
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.a(oaa10),
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.b(obb10),
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.b(obb10),
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.o(oss10),
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.o(oss10),
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.co(oss10c)
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.co(oss10c)
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);
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);
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wire [111:0] odd10;
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wire [(N+1)*4-1:0] odd10;
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wire odd10c;
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wire odd10c;
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|
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BCDSubN #(.N(28)) ubcdsn1
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BCDSubN #(.N(N+1)) ubcdsn1
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(
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(
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.ci(1'b0),
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.ci(1'b0),
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.a(oaa10),
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.a(oaa10),
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.b(obb10),
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.b(obb10),
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.o(odd10),
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.o(odd10),
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| Line 94... |
Line 95... |
// Clock #1
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// Clock #1
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// - decode the input operands
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// - decode the input operands
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg op1;
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reg op1;
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|
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DFPDecomposeReg u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa), .sx(sxa), .exp(xa), .sig(siga), .xz(adn), .vz(az), .inf(aInf), .nan(aNan) );
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DFPDecomposeReg #(.N(N)) u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa), .sx(sxa), .exp(xa), .sig(siga), .xz(adn), .vz(az), .inf(aInf), .nan(aNan) );
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DFPDecomposeReg u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb), .sx(sxb), .exp(xb), .sig(sigb), .xz(bdn), .vz(bz), .inf(bInf), .nan(bNan) );
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DFPDecomposeReg #(.N(N)) u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb), .sx(sxb), .exp(xb), .sig(sigb), .xz(bdn), .vz(bz), .inf(bInf), .nan(bNan) );
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|
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always @(posedge clk)
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always @(posedge clk)
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if (ce) op1 <= op;
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if (ce) op1 <= op;
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|
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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| Line 120... |
Line 121... |
reg realOp2;
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reg realOp2;
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reg op2;
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reg op2;
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reg [15:0] xa2, xb2;
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reg [15:0] xa2, xb2;
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reg az2, bz2;
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reg az2, bz2;
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reg xa_gt_xb2;
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reg xa_gt_xb2;
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reg [107:0] siga2, sigb2;
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reg [N*4-1:0] siga2, sigb2;
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reg sigeq, siga_gt_sigb;
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reg sigeq, siga_gt_sigb;
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reg xa_gt_xb2;
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reg xa_gt_xb2;
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reg expeq;
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reg expeq;
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reg sxo2;
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reg sxo2;
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|
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| Line 176... |
Line 177... |
reg xa_gt_xb3;
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reg xa_gt_xb3;
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reg a_gt_b3;
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reg a_gt_b3;
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reg op3;
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reg op3;
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wire sa3, sb3;
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wire sa3, sb3;
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wire [2:0] rm3;
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wire [2:0] rm3;
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reg [107:0] mfs3;
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reg [N*4-1:0] mfs3;
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|
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always @(posedge clk)
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always @(posedge clk)
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if (ce) resZero3 <= (realOp2 & expeq & sigeq) || // subtract, same magnitude
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if (ce) resZero3 <= (realOp2 & expeq & sigeq) || // subtract, same magnitude
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(az2 & bz2); // both a,b zero
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(az2 & bz2); // both a,b zero
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always @(posedge clk)
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always @(posedge clk)
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| Line 228... |
Line 229... |
|
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// Compute output sign
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// Compute output sign
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reg so4;
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reg so4;
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always @*
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always @*
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case ({resZero3,sa3,op3,sb3}) // synopsys full_case parallel_case
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case ({resZero3,sa3,op3,sb3}) // synopsys full_case parallel_case
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4'b0000: so4 <= 0; // + + + = +
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4'b0000: so4 <= 0; // - + - = -
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4'b0001: so4 <= !a_gt_b3; // + + - = sign of larger
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4'b0001: so4 <= !a_gt_b3; // - + + = sign of larger
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4'b0010: so4 <= !a_gt_b3; // + - + = sign of larger
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4'b0010: so4 <= !a_gt_b3; // - - - = sign of larger
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4'b0011: so4 <= 0; // + - - = +
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4'b0011: so4 <= 0; // - - + = -
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4'b0100: so4 <= a_gt_b3; // - + + = sign of larger
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4'b0100: so4 <= a_gt_b3; // + + - = sign of larger
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4'b0101: so4 <= 1; // - + - = -
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4'b0101: so4 <= 1; // + + + = +
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4'b0110: so4 <= 1; // - - + = -
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4'b0110: so4 <= 1; // + - - = +
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4'b0111: so4 <= a_gt_b3; // - - - = sign of larger
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4'b0111: so4 <= a_gt_b3; // + - + = sign of larger
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4'b1000: so4 <= 0; // A + B, sign = +
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4'b1000: so4 <= 0; // -A + -B, sign = -
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4'b1001: so4 <= rm3==3'd3; // A + -B, sign = + unless rounding down
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4'b1001: so4 <= (rm3==3'd3); // -A + B, sign = + unless rounding down
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4'b1010: so4 <= rm3==3'd3; // A - B, sign = + unless rounding down
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4'b1010: so4 <= (rm3==3'd3); // -A - -B, sign = + unless rounding down
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4'b1011: so4 <= 0; // +A - -B, sign = +
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4'b1011: so4 <= 0; // -A - B, sign = -
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4'b1100: so4 <= rm3==3'd3; // -A + B, sign = + unless rounding down
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4'b1100: so4 <= (rm3==3'd3); // A - B, sign = + unless rounding down
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4'b1101: so4 <= 1; // -A + -B, sign = -
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4'b1101: so4 <= 1; // A + B, sign = +
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4'b1110: so4 <= 1; // -A - +B, sign = -
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4'b1110: so4 <= 1; // A - -B, sign = +
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4'b1111: so4 <= rm3==3'd3; // -A - -B, sign = + unless rounding down
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4'b1111: so4 <= (rm3==3'd3); // -A - -B, sign = + unless rounding down
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endcase
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endcase
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|
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #5
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// Clock #5
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//
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//
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| Line 264... |
Line 265... |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
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// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
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// less) then all of the bits will be shifted out to zero. There is no need to
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// less) then all of the bits will be shifted out to zero. There is no need to
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// keep track of a difference more than 24.
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// keep track of a difference more than 24.
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reg [11:0] xdif6;
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reg [11:0] xdif6;
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wire [107:0] mfs6;
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wire [N*4-1:0] mfs6;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xdif6 <= xdiff5 > 16'h0024 ? 8'h24 : xdiff5[7:0];
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if (ce) xdif6 <= xdiff5 > N ? N : xdiff5[7:0];
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delay #(.WID(108), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
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delay #(.WID(N*4), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
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|
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #7
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// Clock #7
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//
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//
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// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
|
// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
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| Line 279... |
Line 280... |
// reduce the number of regs required.
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// reduce the number of regs required.
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg sticky6;
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reg sticky6;
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wire sticky7;
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wire sticky7;
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wire [7:0] xdif7;
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wire [7:0] xdif7;
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wire [107:0] mfs7;
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wire [N*4-1:0] mfs7;
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wire [7:0] xdif6a = {xdif6[7:4] * 10 + xdif6[3:0],2'b00}; // Convert base then *4
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wire [7:0] xdif6a = {xdif6[7:4] * 10 + xdif6[3:0],2'b00}; // Convert base then *4
|
integer n;
|
integer n;
|
always @* begin
|
always @* begin
|
sticky6 = 1'b0;
|
sticky6 = 1'b0;
|
for (n = 0; n < 96; n = n + 4)
|
for (n = 0; n < N*4; n = n + 4)
|
if (n <= xdif6a)
|
if (n <= xdif6a)
|
sticky6 = sticky6| mfs6[n]|mfs6[n+1]|mfs6[n+2]|mfs6[n+3]; // non-zeero nybble
|
sticky6 = sticky6| mfs6[n]|mfs6[n+1]|mfs6[n+2]|mfs6[n+3]; // non-zeero nybble
|
end
|
end
|
|
|
// register inputs to shifter and shift
|
// register inputs to shifter and shift
|
delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) );
|
delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) );
|
delay1 #(8) d15(.clk(clk), .ce(ce), .i(xdif6a), .o(xdif7) );
|
delay1 #(8) d15(.clk(clk), .ce(ce), .i(xdif6a), .o(xdif7) );
|
delay1 #(108) d14(.clk(clk), .ce(ce), .i(mfs6), .o(mfs7) );
|
delay1 #(N*4) d14(.clk(clk), .ce(ce), .i(mfs6), .o(mfs7) );
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #8
|
// Clock #8
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [111:0] md8;
|
reg [(N+1)*4-1:0] md8;
|
wire [107:0] siga8, sigb8;
|
wire [N*4-1:0] siga8, sigb8;
|
wire xa_gt_xb8;
|
wire xa_gt_xb8;
|
wire a_gt_b8;
|
wire a_gt_b8;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
|
if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
|
|
|
// sync control signals
|
// sync control signals
|
delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
|
delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
|
delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
|
delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
|
delay #(.WID(108), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
|
delay #(.WID(N*4), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
|
delay #(.WID(108), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
|
delay #(.WID(N*4), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
|
delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
|
delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #9
|
// Clock #9
|
// Sort operands and perform add/subtract
|
// Sort operands and perform add/subtract
|
// addition can generate an extra bit, subtract can't go negative
|
// addition can generate an extra bit, subtract can't go negative
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [111:0] oa9, ob9;
|
reg [(N+1)*4-1:0] oa9, ob9;
|
reg a_gt_b9;
|
reg a_gt_b9;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
|
if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
|
if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
|
| Line 328... |
Line 329... |
if (ce) a_gt_b9 <= a_gt_b8;
|
if (ce) a_gt_b9 <= a_gt_b8;
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #10
|
// Clock #10
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [111:0] oaa10;
|
reg [(N+1)*4-1:0] oaa10;
|
reg [111:0] obb10;
|
reg [(N+1)*4-1:0] obb10;
|
wire realOp10;
|
wire realOp10;
|
reg [15:0] xo10;
|
reg [15:0] xo10;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
|
if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
|
| Line 343... |
Line 344... |
delay #(.WID(16), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
|
delay #(.WID(16), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #11
|
// Clock #11
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [111:0] mab11;
|
reg [(N+1)*4-1:0] mab11;
|
reg mab11c;
|
reg mab11c;
|
wire [107:0] siga11, sigb11;
|
wire [N*4-1:0] siga11, sigb11;
|
wire abInf11;
|
wire abInf11;
|
wire aNan11, bNan11;
|
wire aNan11, bNan11;
|
reg xoinf11;
|
reg xoinf11;
|
wire op11;
|
wire op11;
|
|
|
| Line 360... |
Line 361... |
|
|
delay #(.WID(1), .DEP(8)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
|
delay #(.WID(1), .DEP(8)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
|
delay #(.WID(1), .DEP(10)) udly11c (.clk(clk), .ce(ce), .i(aNan), .o(aNan11));
|
delay #(.WID(1), .DEP(10)) udly11c (.clk(clk), .ce(ce), .i(aNan), .o(aNan11));
|
delay #(.WID(1), .DEP(10)) udly11d (.clk(clk), .ce(ce), .i(bNan), .o(bNan11));
|
delay #(.WID(1), .DEP(10)) udly11d (.clk(clk), .ce(ce), .i(bNan), .o(bNan11));
|
delay #(.WID(1), .DEP(3)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
|
delay #(.WID(1), .DEP(3)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
|
delay #(.WID(108), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
|
delay #(.WID(N*4), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
|
delay #(.WID(108), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
|
delay #(.WID(N*4), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
|
|
|
always @(posedge clk)
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always @(posedge clk)
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if (ce) xoinf11 <= xo10==16'h9999;
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if (ce) xoinf11 <= xo10==16'h9999;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #12
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// Clock #12
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [223:0] mo12; // mantissa output
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reg [(N+1)*4*2-1:0] mo12; // mantissa output
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reg [3:0] st12;
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reg [3:0] st12;
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wire sxo11;
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wire sxo11;
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wire so11;
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wire so11;
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delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
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delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
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delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
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delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
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| Line 389... |
Line 390... |
always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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casez({abInf11,aNan11,bNan11,xoinf11})
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casez({abInf11,aNan11,bNan11,xoinf11})
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4'b1???: // inf +/- inf - generate QNaN on subtract, inf on add
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4'b1???: // inf +/- inf - generate QNaN on subtract, inf on add
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if (op11)
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if (op11)
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mo12 <= {4'h9,220'd0};
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mo12 <= {4'h9,{(N+1)*4*2-4{1'd0}}};
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else
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else
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mo12 <= {56{4'h9}};
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mo12 <= {(N+1)*2{4'h9}};
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4'b01??: mo12 <= {4'b0,siga11[107:0],112'd0};
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4'b01??: mo12 <= {4'b0,siga11[107:0],{(N+1)*4{1'd0}}};
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4'b001?: mo12 <= {4'b0,sigb11[107:0],112'd0};
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4'b001?: mo12 <= {4'b0,sigb11[107:0],{(N+1)*4{1'd0}}};
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4'b0001: mo12 <= 224'd0;
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4'b0001: mo12 <= {(N+1)*4*2{1'd0}};
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default: mo12 <= {3'b0,mab11c,mab11,108'd0}; // mab has an extra lead bit and four trailing bits
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default: mo12 <= {3'b0,mab11c,mab11,{N*4{1'd0}}}; // mab has an extra lead bit and four trailing bits
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endcase
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endcase
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #13
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// Clock #13
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire so; // sign output
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wire so; // sign output
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wire [3:0] st;
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wire [3:0] st;
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wire [15:0] xo; // de normalized exponent output
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wire [15:0] xo; // de normalized exponent output
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wire [223:0] mo; // mantissa output
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wire [(N+1)*4*2-1:0] mo; // mantissa output
|
|
|
delay #(.WID(4), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(st12), .o(st[3:0]) );
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delay #(.WID(4), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(st12), .o(st[3:0]) );
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delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(so));
|
delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(so));
|
delay #(.WID(16), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(xo));
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delay #(.WID(16), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(xo));
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delay #(.WID(224), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(mo12), .o(mo) );
|
delay #(.WID((N+1)*4*2), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(mo12), .o(mo) );
|
|
|
assign o = {st,xo,mo};
|
assign o = {st,xo,mo};
|
|
|
endmodule
|
endmodule
|
|
|
|
|
module DFPAddsubnr(clk, ce, rm, op, a, b, o);
|
module DFPAddsubnr(clk, ce, rm, op, a, b, o);
|
|
parameter N=33;
|
input clk; // system clock
|
input clk; // system clock
|
input ce; // core clock enable
|
input ce; // core clock enable
|
input [2:0] rm; // rounding mode
|
input [2:0] rm; // rounding mode
|
input op; // operation 0 = add, 1 = subtract
|
input op; // operation 0 = add, 1 = subtract
|
input [127:0] a; // operand a
|
input [N*4+16+4-1:0] a; // operand a
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input [127:0] b; // operand b
|
input [N*4+16+4-1:0] b; // operand b
|
output [127:0] o; // output
|
output [N*4+16+4-1:0] o; // output
|
|
|
wire [243:0] o1;
|
wire [(N+1)*4*2+16+4-1:0] o1;
|
wire [131:0] fpn0;
|
wire [N*4+16+4-1+4:0] fpn0;
|
|
|
DFPAddsub u1 (clk, ce, rm, op, a, b, o1);
|
DFPAddsub u1 (clk, ce, rm, op, a, b, o1);
|
DFPNormalize u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
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DFPNormalize u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
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DFPRound u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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DFPRound u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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