| Line 1... |
Line 1... |
// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020-2021 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// DFPAddsub.sv
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// DFPAddsub.sv
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| Line 44... |
Line 44... |
input op;
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input op;
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input DFP128 a;
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input DFP128 a;
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input DFP128 b;
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input DFP128 b;
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output DFP128UD o;
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output DFP128UD o;
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localparam N=34; // number of BCD digits
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localparam N=34; // number of BCD digits
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localparam RIP_STAGES = 3;
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parameter TRUE = 1'b1;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter FALSE = 1'b0;
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DFP128U au;
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DFP128U au;
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DFP128U bu;
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DFP128U bu;
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wire sa, sb;
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wire sxa, sxb;
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wire adn, bdn;
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wire xainf, xbinf;
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wire ainf, binf;
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wire aNan, bNan;
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wire [13:0] xa, xb;
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wire [N*4-1:0] siga, sigb;
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DFPUnpack128 u00 (a, au);
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DFPUnpack128 u00 (a, au);
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DFPUnpack128 u01 (b, bu);
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DFPUnpack128 u01 (b, bu);
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reg [(N+1)*4-1:0] oaa10;
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reg [(N+1)*4-1:0] obb10;
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wire [(N+1)*4-1:0] oss10;
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wire [(N+1)*4-1:0] oss10;
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wire oss10c;
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wire oss10c;
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BCDAddN #(.N(N+1)) ubcdan1
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BCDAdd8NClk #(.N((N+2)/2)) ubcdadn1
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(
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(
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.ci(1'b0),
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.clk(clk),
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.a(oaa10),
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.a({8'h00,oaa10}),
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.b(obb10),
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.b({8'h00,obb10}),
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.o(oss10),
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.o(oss10),
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.ci(1'b0),
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.co(oss10c)
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.co(oss10c)
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);
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);
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wire [(N+1)*4-1:0] odd10;
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wire [(N+1)*4-1:0] odd10;
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wire odd10c;
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wire odd10c;
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BCDSubN #(.N(N+1)) ubcdsn1
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BCDSub8NClk #(.N((N+2)/2)) ubcdsdn1
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(
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(
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.ci(1'b0),
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.clk(clk),
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.a(oaa10),
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.a({8'h00,oaa10}),
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.b(obb10),
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.b({8'h00,obb10}),
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.o(odd10),
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.o(odd10),
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.ci(1'b0),
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.co(odd10c)
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.co(odd10c)
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);
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);
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #1
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// Clock #1
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg op1;
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reg op1;
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reg az, bz;
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reg az, bz;
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always @(posedge clk)
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always_ff @(posedge clk)
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op1 <= op;
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op1 <= op;
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always @(posedge clk)
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always_ff @(posedge clk)
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az <= au.sig==136'd0 && au.exp==14'd0;
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az <= au.sig==136'd0 && au.exp==14'd0;
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always @(posedge clk)
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always_ff @(posedge clk)
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bz <= bu.sig==136'd0 && bu.exp==14'd0;
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bz <= bu.sig==136'd0 && bu.exp==14'd0;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #2
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// Clock #2
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//
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//
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| Line 124... |
Line 121... |
reg sigeq, siga_gt_sigb;
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reg sigeq, siga_gt_sigb;
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reg xa_gt_xb2;
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reg xa_gt_xb2;
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reg expeq;
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reg expeq;
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reg sxo2;
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reg sxo2;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) realOp2 = op1 ^ au.sign ^ bu.sign;
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if (ce) realOp2 = op1 ^ au.sign ^ bu.sign;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) op2 <= op1;
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if (ce) op2 <= op1;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xa2 <= au.exp;
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if (ce) xa2 <= au.exp;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xb2 <= bu.exp;
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if (ce) xb2 <= bu.exp;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) siga2 <= au.sig;
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if (ce) siga2 <= au.sig;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) sigb2 <= bu.sig;
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if (ce) sigb2 <= bu.sig;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) az2 <= az;
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if (ce) az2 <= az;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) bz2 <= bz;
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if (ce) bz2 <= bz;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce)
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if (ce)
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xa_gt_xb2 <= au.exp > bu.exp;
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xa_gt_xb2 <= au.exp > bu.exp;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) sigeq <= au.sig==bu.sig;
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if (ce) sigeq <= au.sig==bu.sig;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) siga_gt_sigb <= au.sig > bu.sig;
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if (ce) siga_gt_sigb <= au.sig > bu.sig;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) expeq <= au.exp==bu.exp;
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if (ce) expeq <= au.exp==bu.exp;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #3
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// Clock #3
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//
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//
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| Line 168... |
Line 165... |
reg op3;
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reg op3;
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wire sa3, sb3;
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wire sa3, sb3;
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wire [2:0] rm3;
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wire [2:0] rm3;
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reg [N*4-1:0] mfs3;
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reg [N*4-1:0] mfs3;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) resZero3 <= (realOp2 & expeq & sigeq) || // subtract, same magnitude
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if (ce) resZero3 <= (realOp2 & expeq & sigeq) || // subtract, same magnitude
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(az2 & bz2); // both a,b zero
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(az2 & bz2); // both a,b zero
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xa3 <= xa2;
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if (ce) xa3 <= xa2;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xb3 <= xb2;
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if (ce) xb3 <= xb2;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xa_gt_xb3 <= xa_gt_xb2;
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if (ce) xa_gt_xb3 <= xa_gt_xb2;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) a_gt_b3 <= xa_gt_xb2 | (expeq & siga_gt_sigb);
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if (ce) a_gt_b3 <= xa_gt_xb2 | (expeq & siga_gt_sigb);
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) op3 <= op2;
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if (ce) op3 <= op2;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) mfs3 = xa_gt_xb2 ? sigb2 : siga2;
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if (ce) mfs3 = xa_gt_xb2 ? sigb2 : siga2;
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delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(au.sign), .o(sa3));
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ft_delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(au.sign), .o(sa3));
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delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(bu.sign), .o(sb3));
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ft_delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(bu.sign), .o(sb3));
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delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
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ft_delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
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delay #(.WID(1), .DEP(2)) udly3f (.clk(clk), .ce(ce), .i(aInf), .o(aInf3));
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ft_delay #(.WID(1), .DEP(2)) udly3f (.clk(clk), .ce(ce), .i(aInf), .o(aInf3));
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delay #(.WID(1), .DEP(2)) udly3g (.clk(clk), .ce(ce), .i(bInf), .o(bInf3));
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ft_delay #(.WID(1), .DEP(2)) udly3g (.clk(clk), .ce(ce), .i(bInf), .o(bInf3));
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #4
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// Clock #4
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//
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//
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// Compute output exponent
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// Compute output exponent
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| Line 205... |
Line 202... |
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reg [13:0] xa4, xb4;
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reg [13:0] xa4, xb4;
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reg [13:0] xo4;
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reg [13:0] xo4;
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reg xa_gt_xb4;
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reg xa_gt_xb4;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xa4 <= xa3;
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if (ce) xa4 <= xa3;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xb4 <= xb3;
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if (ce) xb4 <= xb3;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xo4 <= resZero3 ? 14'd0 : xa_gt_xb3 ? xa3 : xb3;
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if (ce) xo4 <= resZero3 ? 14'd0 : xa_gt_xb3 ? xa3 : xb3;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xa_gt_xb4 <= xa_gt_xb3;
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if (ce) xa_gt_xb4 <= xa_gt_xb3;
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// Compute output sign
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// Compute output sign
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reg so4;
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reg so4;
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always @*
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always_comb
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case ({resZero3,sa3,op3,sb3}) // synopsys full_case parallel_case
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case ({resZero3,sa3,op3,sb3}) // synopsys full_case parallel_case
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4'b0000: so4 <= 0; // + + + = +
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4'b0000: so4 <= 0; // + + + = +
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4'b0001: so4 <= !a_gt_b3; // + + - = sign of larger
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4'b0001: so4 <= !a_gt_b3; // + + - = sign of larger
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4'b0010: so4 <= !a_gt_b3; // + - + = sign of larger
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4'b0010: so4 <= !a_gt_b3; // + - + = sign of larger
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4'b0011: so4 <= 0; // + - - = +
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4'b0011: so4 <= 0; // + - - = +
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| Line 242... |
Line 239... |
// Clock #5
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// Clock #5
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//
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//
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// Compute the difference in exponents, provides shift amount
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// Compute the difference in exponents, provides shift amount
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [13:0] xdiff5;
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reg [13:0] xdiff5;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xdiff5 <= xa_gt_xb4 ? xa4 - xb4 : xb4 - xa4;
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if (ce) xdiff5 <= xa_gt_xb4 ? xa4 - xb4 : xb4 - xa4;
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|
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #6
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// Clock #6
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//
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//
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| Line 255... |
Line 252... |
// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
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// If the difference in the exponent is 24 or greater (assuming 24 nybble dfp or
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// less) then all of the bits will be shifted out to zero. There is no need to
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// less) then all of the bits will be shifted out to zero. There is no need to
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// keep track of a difference more than 24.
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// keep track of a difference more than 24.
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reg [6:0] xdif6;
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reg [6:0] xdif6;
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wire [N*4-1:0] mfs6;
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wire [N*4-1:0] mfs6;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) xdif6 <= xdiff5 > N ? N : xdiff5[6:0];
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if (ce) xdif6 <= xdiff5 > N ? N : xdiff5[6:0];
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delay #(.WID(N*4), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
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ft_delay #(.WID(N*4), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
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|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #7
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// Clock #7
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//
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//
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// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
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// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
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| Line 272... |
Line 269... |
wire sticky7;
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wire sticky7;
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wire [7:0] xdif7;
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wire [7:0] xdif7;
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wire [N*4-1:0] mfs7;
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wire [N*4-1:0] mfs7;
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wire [8:0] xdif6a = {xdif6,2'b00}; // *4
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wire [8:0] xdif6a = {xdif6,2'b00}; // *4
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integer n;
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integer n;
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always @* begin
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always @*
|
|
begin
|
sticky6 = 1'b0;
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sticky6 = 1'b0;
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for (n = 0; n < N*4; n = n + 4)
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for (n = 0; n < N*4; n = n + 4)
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if (n <= xdif6a)
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if (n <= xdif6a)
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sticky6 = sticky6| mfs6[n]|mfs6[n+1]|mfs6[n+2]|mfs6[n+3]; // non-zero nybble
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sticky6 = sticky6| mfs6[n]|mfs6[n+1]|mfs6[n+2]|mfs6[n+3]; // non-zero nybble
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end
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end
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| Line 291... |
Line 289... |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [(N+1)*4-1:0] md8;
|
reg [(N+1)*4-1:0] md8;
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wire [N*4-1:0] siga8, sigb8;
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wire [N*4-1:0] siga8, sigb8;
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wire xa_gt_xb8;
|
wire xa_gt_xb8;
|
wire a_gt_b8;
|
wire a_gt_b8;
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always @(posedge clk)
|
always_ff @(posedge clk)
|
if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
|
if (ce) md8 <= ({mfs7,4'b0} >> xdif7)|sticky7; // xdif7 is a multiple of four
|
|
|
// sync control signals
|
// sync control signals
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delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
|
ft_delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
|
delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
|
ft_delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
|
delay #(.WID(N*4), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
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ft_delay #(.WID(N*4), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(siga2), .o(siga8));
|
delay #(.WID(N*4), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
|
ft_delay #(.WID(N*4), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(sigb2), .o(sigb8));
|
delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
|
ft_delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #9
|
// Clock #9
|
// Sort operands and perform add/subtract
|
// Sort operands and perform add/subtract
|
// addition can generate an extra bit, subtract can't go negative
|
// addition can generate an extra bit, subtract can't go negative
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [(N+1)*4-1:0] oa9, ob9;
|
reg [(N+1)*4-1:0] oa9, ob9;
|
reg a_gt_b9;
|
reg a_gt_b9;
|
always @(posedge clk)
|
always_ff @(posedge clk)
|
if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
|
if (ce) oa9 <= xa_gt_xb8 ? {siga8,4'b0} : md8;
|
always @(posedge clk)
|
always_ff @(posedge clk)
|
if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
|
if (ce) ob9 <= xa_gt_xb8 ? md8 : {sigb8,4'b0};
|
always @(posedge clk)
|
always_ff @(posedge clk)
|
if (ce) a_gt_b9 <= a_gt_b8;
|
if (ce) a_gt_b9 <= a_gt_b8;
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #10
|
// Clock #10
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [(N+1)*4-1:0] oaa10;
|
|
reg [(N+1)*4-1:0] obb10;
|
|
wire realOp10;
|
wire realOp10;
|
reg [13:0] xo10;
|
reg [13:0] xo10;
|
|
|
always @(posedge clk)
|
always_ff @(posedge clk)
|
if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
|
if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
|
always @(posedge clk)
|
always_ff @(posedge clk)
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if (ce) obb10 <= a_gt_b9 ? ob9 : oa9;
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if (ce) obb10 <= a_gt_b9 ? ob9 : oa9;
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delay #(.WID(1), .DEP(8)) udly10a (.clk(clk), .ce(ce), .i(realOp2), .o(realOp10));
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ft_delay #(.WID(1), .DEP(8)) udly10a (.clk(clk), .ce(ce), .i(realOp2), .o(realOp10));
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delay #(.WID(14), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
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ft_delay #(.WID(14), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #11
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// Clock #11
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [(N+1)*4-1:0] mab11;
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wire [(N+1)*4-1:0] mab11;
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reg mab11c;
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wire mab11c;
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wire [N*4-1:0] siga11, sigb11;
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wire [N*4-1:0] siga11, sigb11;
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wire abInf11;
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wire abInf11;
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wire aNan11, bNan11;
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wire aNan11, bNan11;
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reg xoinf11;
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wire xoinf11;
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wire op11;
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wire op11;
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always @(posedge clk)
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ft_delay #(.WID(1), .DEP(8+RIP_STAGES)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
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if (ce) mab11 <= realOp10 ? odd10 : oss10;
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ft_delay #(.WID(1), .DEP(10+RIP_STAGES)) udly11c (.clk(clk), .ce(ce), .i(au.nan), .o(aNan11));
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always @(posedge clk)
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ft_delay #(.WID(1), .DEP(10+RIP_STAGES)) udly11d (.clk(clk), .ce(ce), .i(bu.nan), .o(bNan11));
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if (ce) mab11c <= realOp10 ? odd10c : oss10c;
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ft_delay #(.WID(1), .DEP(3+RIP_STAGES)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
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ft_delay #(.WID(N*4), .DEP(3+RIP_STAGES)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
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delay #(.WID(1), .DEP(8)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
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ft_delay #(.WID(N*4), .DEP(3+RIP_STAGES)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
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delay #(.WID(1), .DEP(10)) udly11c (.clk(clk), .ce(ce), .i(aNan), .o(aNan11));
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ft_delay #(.WID(1), .DEP(1+RIP_STAGES)) udly11h (.clk(clk), .ce(ce), .i(xo10==14'h2FFF), .o(xoinf11));
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delay #(.WID(1), .DEP(10)) udly11d (.clk(clk), .ce(ce), .i(bNan), .o(bNan11));
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ft_delay #(.WID((N+1)*4+1), .DEP(1+RIP_STAGES)) udly11i (.clk(clk), .ce(ce), .i(realOp10 ? {odd10c,odd10} : {oss10c,oss10}), .o({mab11c,mab11}));
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delay #(.WID(1), .DEP(3)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
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delay #(.WID(N*4), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(siga8), .o(siga11));
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delay #(.WID(N*4), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(sigb8), .o(sigb11));
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always @(posedge clk)
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if (ce) xoinf11 <= xo10==14'h2FFF;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #12
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// Clock #12+RIP_STAGES
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [(N+1)*4*2-1:0] mo12; // mantissa output
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reg [(N+1)*4*2-1:0] mo12; // mantissa output
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reg nan12;
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reg nan12;
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reg qnan12;
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reg qnan12;
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reg infinity12;
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reg infinity12;
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wire sxo11;
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wire sxo11;
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wire so11;
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wire so11;
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delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
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ft_delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
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delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
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ft_delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce)
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if (ce)
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nan12 <= aNan11|bNan11;
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nan12 <= aNan11|bNan11;
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce) begin
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if (ce) begin
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infinity12 <= 1'b0;
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infinity12 <= 1'b0;
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qnan12 <= 1'b0;
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qnan12 <= 1'b0;
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casez({abInf11,aNan11,bNan11,xoinf11})
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casez({abInf11,aNan11,bNan11,xoinf11})
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4'b1???: // inf +/- inf - generate QNaN on subtract, inf on add
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4'b1???: // inf +/- inf - generate QNaN on subtract, inf on add
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| Line 400... |
Line 390... |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire so; // sign output
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wire so; // sign output
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wire [15:0] xo; // de normalized exponent output
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wire [15:0] xo; // de normalized exponent output
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wire [(N+1)*4*2-1:0] mo; // mantissa output
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wire [(N+1)*4*2-1:0] mo; // mantissa output
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delay #(.WID(1), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(nan12), .o(o.nan) );
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ft_delay #(.WID(1), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(nan12), .o(o.nan) );
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delay #(.WID(1), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(qnan12), .o(o.qnan) );
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ft_delay #(.WID(1), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(qnan12), .o(o.qnan) );
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delay #(.WID(1), .DEP(1)) u13e (.clk(clk), .ce(ce), .i(infinity12), .o(o.infinity) );
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ft_delay #(.WID(1), .DEP(1)) u13e (.clk(clk), .ce(ce), .i(infinity12), .o(o.infinity) );
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delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(o.sign));
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ft_delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(o.sign));
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delay #(.WID(14), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(o.exp));
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ft_delay #(.WID(14), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(o.exp));
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delay #(.WID((N+1)*4*2), .DEP(1)) u13f (.clk(clk), .ce(ce), .i(mo12), .o(o.sig));
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ft_delay #(.WID((N+1)*4*2), .DEP(1)) u13f (.clk(clk), .ce(ce), .i(mo12), .o(o.sig));
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delay #(.WID(1), .DEP(1)) udly13g (.clk(clk), .ce(ce), .i(1'b0), .o(o.snan));
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ft_delay #(.WID(1), .DEP(1)) udly13g (.clk(clk), .ce(ce), .i(1'b0), .o(o.snan));
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endmodule
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endmodule
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module DFPAddsub128nr(clk, ce, rm, op, a, b, o);
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module DFPAddsub128nr(clk, ce, rm, op, a, b, o);
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