| Line 74... |
Line 74... |
);
|
);
|
|
|
wire [(N+1)*4-1:0] odd10;
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wire [(N+1)*4-1:0] odd10;
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wire odd10c;
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wire odd10c;
|
|
|
|
BCDSubtract #(N+2) ubcdsubn1
|
|
(
|
|
.clk(clk),
|
|
.a({8'h00,oaa10}),
|
|
.b({8'h00,obb10}),
|
|
.o(odd10),
|
|
.co(odd10c)
|
|
);
|
|
/*
|
BCDSub8NClk #(.N((N+2)/2)) ubcdsdn1
|
BCDSub8NClk #(.N((N+2)/2)) ubcdsdn1
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.a({8'h00,oaa10}),
|
.a({8'h00,oaa10}),
|
.b({8'h00,obb10}),
|
.b({8'h00,obb10}),
|
.o(odd10),
|
.o(odd10),
|
.ci(1'b0),
|
.ci(1'b0),
|
.co(odd10c)
|
.co(odd10c)
|
);
|
);
|
|
*/
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #1
|
// Clock #1
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg op1;
|
reg op1;
|
reg az, bz;
|
reg az, bz;
|
| Line 119... |
Line 128... |
reg az2, bz2;
|
reg az2, bz2;
|
reg xa_gt_xb2;
|
reg xa_gt_xb2;
|
reg [N*4-1:0] siga2, sigb2;
|
reg [N*4-1:0] siga2, sigb2;
|
reg sigeq, siga_gt_sigb;
|
reg sigeq, siga_gt_sigb;
|
reg expeq;
|
reg expeq;
|
reg sxo2;
|
|
|
|
always_ff @(posedge clk)
|
always_ff @(posedge clk)
|
if (ce) realOp2 = op1 ^ au.sign ^ bu.sign;
|
if (ce) realOp2 = op1 ^ au.sign ^ bu.sign;
|
always_ff @(posedge clk)
|
always_ff @(posedge clk)
|
if (ce) op2 <= op1;
|
if (ce) op2 <= op1;
|
| Line 157... |
Line 165... |
// Determine which fraction to denormalize
|
// Determine which fraction to denormalize
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//
|
//
|
reg [11:0] xa3, xb3;
|
reg [11:0] xa3, xb3;
|
reg resZero3;
|
reg resZero3;
|
wire xaInf3, xbInf3;
|
|
reg xa_gt_xb3;
|
reg xa_gt_xb3;
|
reg a_gt_b3;
|
reg a_gt_b3;
|
reg op3;
|
reg op3;
|
wire sa3, sb3;
|
wire sa3, sb3;
|
wire [2:0] rm3;
|
wire [2:0] rm3;
|
| Line 184... |
Line 191... |
if (ce) mfs3 = xa_gt_xb2 ? sigb2 : siga2;
|
if (ce) mfs3 = xa_gt_xb2 ? sigb2 : siga2;
|
|
|
ft_delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(au.sign), .o(sa3));
|
ft_delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(au.sign), .o(sa3));
|
ft_delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(bu.sign), .o(sb3));
|
ft_delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(bu.sign), .o(sb3));
|
ft_delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
|
ft_delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
|
ft_delay #(.WID(1), .DEP(2)) udly3f (.clk(clk), .ce(ce), .i(aInf), .o(aInf3));
|
ft_delay #(.WID(1), .DEP(3)) udly3f (.clk(clk), .ce(ce), .i(au.infinity), .o(aInf3));
|
ft_delay #(.WID(1), .DEP(2)) udly3g (.clk(clk), .ce(ce), .i(bInf), .o(bInf3));
|
ft_delay #(.WID(1), .DEP(3)) udly3g (.clk(clk), .ce(ce), .i(bu.infinity), .o(bInf3));
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #4
|
// Clock #4
|
//
|
//
|
// Compute output exponent
|
// Compute output exponent
|
| Line 353... |
Line 360... |
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [(N+1)*4*2-1:0] mo12; // mantissa output
|
reg [(N+1)*4*2-1:0] mo12; // mantissa output
|
reg nan12;
|
reg nan12;
|
reg qnan12;
|
reg qnan12;
|
reg infinity12;
|
reg infinity12;
|
wire sxo11;
|
|
wire so11;
|
wire so11;
|
ft_delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
|
|
ft_delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
|
ft_delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
|
|
|
always_ff @(posedge clk)
|
always_ff @(posedge clk)
|
if (ce)
|
if (ce)
|
nan12 <= aNan11|bNan11;
|
nan12 <= aNan11|bNan11;
|
| Line 386... |
Line 391... |
end
|
end
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock #13
|
// Clock #13
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
wire so; // sign output
|
|
wire [13:0] xo; // de normalized exponent output
|
|
wire [(N+1)*4*2-1:0] mo; // mantissa output
|
|
|
|
ft_delay #(.WID(1), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(nan12), .o(o.nan) );
|
ft_delay #(.WID(1), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(nan12), .o(o.nan) );
|
ft_delay #(.WID(1), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(qnan12), .o(o.qnan) );
|
ft_delay #(.WID(1), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(qnan12), .o(o.qnan) );
|
ft_delay #(.WID(1), .DEP(1)) u13e (.clk(clk), .ce(ce), .i(infinity12), .o(o.infinity) );
|
ft_delay #(.WID(1), .DEP(1)) u13e (.clk(clk), .ce(ce), .i(infinity12), .o(o.infinity) );
|
ft_delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(o.sign));
|
ft_delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(o.sign));
|
