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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPDecompose.sv] - Diff between revs 53 and 55

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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
//
 
//
 
// ============================================================================
 
// ============================================================================
 
 
 
 
 
module DFPDecompose(i, sgn, sx, exp, sig, xz, vz, inf, nan);
 
module DFPDecompose(i, sgn, sx, exp, sig, xz, vz, inf, nan);
 
input [127:0] i;
 
parameter N=33;
 
 
 
input [(N*4)+16+4-1:0] i;
 
output sgn;
 
output sgn;
 
output sx;
 
output sx;
 
output [15:0] exp;
 
output [15:0] exp;
 
output [107:0] sig;
 
output [N*4-1:0] sig;
 
output xz;
 
output xz;
 
output vz;
 
output vz;
 
output inf;
 
output inf;
 
output nan;
 
output nan;
 
 
 
 
 
assign nan = i[127];
 
assign nan = i[N*4+19];
 
assign sgn = i[126];
 
assign sgn = i[N*4+18];
 
assign inf = i[125];
 
assign inf = i[N*4+17];
 
assign sx = i[124];
 
assign sx = i[N*4+16];
 
assign exp = i[123:108];
 
assign exp = i[N*4+15:N*4];
 
assign sig = i[107:0];
 
assign sig = i[N*4-1:0];
 
assign xz = ~|exp;
 
assign xz = ~|exp;
 
assign vz = ~|{exp,sig};
 
assign vz = ~|{exp,sig};
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
module DFPDecomposeReg(clk, ce, i, sgn, sx, exp, sig, xz, vz, inf, nan);
 
module DFPDecomposeReg(clk, ce, i, sgn, sx, exp, sig, xz, vz, inf, nan);
 
 
 
parameter N=33;
 
input clk;
 
input clk;
 
input ce;
 
input ce;
 
input [127:0] i;
 
input [N*4+16+4-1:0] i;
 
output reg sgn;
 
output reg sgn;
 
output reg sx;
 
output reg sx;
 
output reg [15:0] exp;
 
output reg [15:0] exp;
 
output reg [107:0] sig;
 
output reg [N*4-1:0] sig;
 
output reg xz;
 
output reg xz;
 
output reg vz;
 
output reg vz;
 
output reg inf;
 
output reg inf;
 
output reg nan;
 
output reg nan;
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) begin
 
        if (ce) begin
 
                nan <= i[127];
 
                nan <= i[N*4+19];
 
                sgn <= i[126];
 
                sgn <= i[N*4+18];
 
                inf <= i[125];
 
                inf <= i[N*4+17];
 
                sx <= i[124];
 
                sx <= i[N*4+16];
 
                exp <= i[123:108];
 
                exp <= i[N*4+15:N*4];
 
                sig <= i[107:0];
 
                sig <= i[N*4-1:0];
 
                xz <= ~|exp;
 
                xz <= ~|exp;
 
                vz <= ~|{exp,sig};
 
                vz <= ~|{exp,sig};
 
        end
 
        end
 
 
 
 
 
endmodule
 
endmodule

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