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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPDivide.sv] - Diff between revs 54 and 55

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// ============================================================================
// ============================================================================
 
 
import fp::*;
import fp::*;
 
 
module DFPDivide(rst, clk, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
module DFPDivide(rst, clk, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
 
parameter N=33;
// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
input rst;
input rst;
input clk;
input clk;
input ce;
input ce;
input ld;
input ld;
input op;
input op;
input [127:0] a, b;
input  [N*4+16+4-1:0] a, b;
output [243:0] o;
output [(N+1)*4*2+16+4-1:0] o;
output reg done;
output reg done;
output sign_exe;
output sign_exe;
output overflow;
output overflow;
output underflow;
output underflow;
 
 
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reg     underflow=0;
reg     underflow=0;
 
 
reg so, sxo;
reg so, sxo;
reg [3:0] st;
reg [3:0] st;
reg [15:0] xo;
reg [15:0] xo;
reg [223:0] mo;
reg [(N+1)*4*2-1:0] mo;
assign o = {st,xo,mo};
assign o = {st,xo,mo};
 
 
// constants
// constants
wire [15:0] infXp = 16'h9999;   // infinite / NaN - all ones
wire [15:0] infXp = 16'h9999;   // infinite / NaN - all ones
// The following is the value for an exponent of zero, with the offset
// The following is the value for an exponent of zero, with the offset
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
// The following is a template for a quiet nan. (MSB=1)
// The following is a template for a quiet nan. (MSB=1)
wire [107:0] qNaN  = {4'h1,{104{1'b0}}};
wire [N*4-1:0] qNaN  = {4'h1,{(N-1)*4{1'b0}}};
 
 
// variables
// variables
wire [231:0] divo;
wire [(N+2)*4*2-1:0] divo;
 
 
// Operands
// Operands
wire sa, sb;                    // sign bit
wire sa, sb;                    // sign bit
wire sxa, sxb;
wire sxa, sxb;
wire [15:0] xa, xb;     // exponent bits
wire [15:0] xa, xb;     // exponent bits
wire [107:0] siga, sigb;
wire [N*4-1:0] siga, sigb;
wire a_dn, b_dn;                        // a/b is denormalized
wire a_dn, b_dn;                        // a/b is denormalized
wire az, bz;
wire az, bz;
wire aInf, bInf;
wire aInf, bInf;
wire aNan,bNan;
wire aNan,bNan;
wire done1;
wire done1;
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// Clock #2 to N
// Clock #2 to N
// - calculate fraction
// - calculate fraction
// -----------------------------------------------------------
// -----------------------------------------------------------
wire done3a,done3;
wire done3a,done3;
// Perform divide
// Perform divide
dfdiv #(108+8) u2 (.clk(clk), .ld(ld1), .a({siga,8'b0}), .b({sigb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
dfdiv #(N+2) u2 (.clk(clk), .ld(ld1), .a({siga,8'b0}), .b({sigb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
wire [7:0] lzcnt_bin = lzcnt[3:0] + (lzcnt[7:4] * 10);
wire [7:0] lzcnt_bin = lzcnt[3:0] + (lzcnt[7:4] * 10);
wire [231:0] divo1 = divo[231:0] << ({lzcnt_bin,2'b0}+(FPWID+44));
wire [(N+2)*4*2-1:0] divo1 = divo[(N+2)*4*2-1:0] << ({lzcnt_bin,2'b0}+(N*4));//WAS FPWID=128?+44
delay #(.WID(1), .DEP(3)) u3 (.clk(clk), .ce(ce), .i(done1), .o(done3a));
delay #(.WID(1), .DEP(3)) u3 (.clk(clk), .ce(ce), .i(done1), .o(done3a));
assign done3 = done1&done3a;
assign done3 = done1&done3a;
 
 
// -----------------------------------------------------------
// -----------------------------------------------------------
// Clock #N+1
// Clock #N+1
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                5'b00001:               xo <= 1'd0;             // underflow
                5'b00001:               xo <= 1'd0;             // underflow
                default:                xo <= ex1;      // normal or underflow: passthru neg. exp. for normalization
                default:                xo <= ex1;      // normal or underflow: passthru neg. exp. for normalization
                endcase
                endcase
 
 
                casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
                casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
                8'b1???????:  begin mo <= {4'h1,a[107:0],{111{1'b0}}}; st[3] <= 1'b1; end
                8'b1???????:  begin mo <= {4'h1,a[N*4-1:0],{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end
                8'b01??????:  begin mo <= {4'h1,b[107:0],{111{1'b0}}}; st[3] <= 1'b1; end
                8'b01??????:  begin mo <= {4'h1,b[N*4-1:0],{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end
                8'b001?????:    begin mo <= {4'h1,qNaN[107:0]|{aInf,1'b0}|{az,bz},{1111{1'b0}}}; st[3] <= 1'b1; end
                8'b001?????:    begin mo <= {4'h1,qNaN[N*4-1:0]|{aInf,1'b0}|{az,bz},{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end
                8'b0001????:    begin mo <= 224'd0;     st[3] <= 1'b0; end      // div by inf
                8'b0001????:    begin mo <= {(N+1)*4*2-1{1'd0}};        st[3] <= 1'b0; end      // div by inf
                8'b00001???:    begin mo <= 224'd0;     st[3] <= 1'b0; end      // div by zero
                8'b00001???:    begin mo <= {(N+1)*4*2-1{1'd0}};        st[3] <= 1'b0; end      // div by zero
                8'b000001??:    begin mo <= 224'd0;     st[3] <= 1'b0; end      // Inf exponent
                8'b000001??:    begin mo <= {(N+1)*4*2-1{1'd0}};        st[3] <= 1'b0; end      // Inf exponent
                8'b0000001?:    begin mo <= {4'h1,qNaN|`QINFDIV,{111{1'b0}}};   st[3] <= 1'b1; end      // infinity / infinity
                8'b0000001?:    begin mo <= {4'h1,qNaN|`QINFDIV,{(N+1)*4-1{1'b0}}};     st[3] <= 1'b1; end      // infinity / infinity
                8'b00000001:    begin mo <= {4'h1,qNaN|`QZEROZERO,{111{1'b0}}}; st[3] <= 1'b1; end      // zero / zero
                8'b00000001:    begin mo <= {4'h1,qNaN|`QZEROZERO,{(N+1)*4-1{1'b0}}};   st[3] <= 1'b1; end      // zero / zero
                default:                begin mo <= divo1[231:8];       st[3] <= 1'b0; end      // plain div
                default:                begin mo <= divo1[(N+2)*4*2-1:8];       st[3] <= 1'b0; end      // plain div
                endcase
                endcase
 
 
                st[0] <= sxo;
                st[0] <= sxo;
                st[1] <= aInf;
                st[1] <= aInf;
                st[2] <= ~(sa ^ sb);
                st[2] <= ~(sa ^ sb);
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end
end
 
 
endmodule
endmodule
 
 
module DFPDividenr(rst, clk, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
module DFPDividenr(rst, clk, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
 
parameter N=33;
input rst;
input rst;
input clk;
input clk;
input ce;
input ce;
input ld;
input ld;
input op;
input op;
input  [127:0] a, b;
input  [N*4+16+4-1:0] a, b;
output [127:0] o;
output [N*4+16+4-1:0] o;
input [2:0] rm;
input [2:0] rm;
output sign_exe;
output sign_exe;
output done;
output done;
output inf;
output inf;
output overflow;
output overflow;
output underflow;
output underflow;
 
 
wire [243:0] o1;
wire [(N+1)*4*2+16+4-1:0] o1;
wire sign_exe1, inf1, overflow1, underflow1;
wire sign_exe1, inf1, overflow1, underflow1;
wire [131:0] fpn0;
wire [N*4+16+4-1+4:0] fpn0;
wire done1, done1a;
wire done1, done1a;
 
 
DFPDivide    #(FPWID) u1 (rst, clk, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
DFPDivide    #(.N(N)) u1 (rst, clk, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
DFPNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
DFPNormalize #(.N(N)) u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
DFPRound     #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
DFPRound     #(.N(N)) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
delay   #(.WID(1),.DEP(11))   u8(.clk(clk), .ce(ce), .i(done1), .o(done1a));
delay   #(.WID(1),.DEP(11))   u8(.clk(clk), .ce(ce), .i(done1), .o(done1a));

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