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// ============================================================================
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// ============================================================================
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import fp::*;
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import fp::*;
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module DFPDivide(rst, clk, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
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module DFPDivide(rst, clk, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
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parameter N=33;
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// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
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// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
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input rst;
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input rst;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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input op;
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input op;
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input [127:0] a, b;
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input [N*4+16+4-1:0] a, b;
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output [243:0] o;
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output [(N+1)*4*2+16+4-1:0] o;
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output reg done;
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output reg done;
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output sign_exe;
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output sign_exe;
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output overflow;
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output overflow;
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output underflow;
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output underflow;
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reg underflow=0;
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reg underflow=0;
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reg so, sxo;
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reg so, sxo;
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reg [3:0] st;
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reg [3:0] st;
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reg [15:0] xo;
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reg [15:0] xo;
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reg [223:0] mo;
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reg [(N+1)*4*2-1:0] mo;
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assign o = {st,xo,mo};
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assign o = {st,xo,mo};
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// constants
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// constants
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wire [15:0] infXp = 16'h9999; // infinite / NaN - all ones
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wire [15:0] infXp = 16'h9999; // infinite / NaN - all ones
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// The following is the value for an exponent of zero, with the offset
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// The following is the value for an exponent of zero, with the offset
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// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
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// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
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// The following is a template for a quiet nan. (MSB=1)
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// The following is a template for a quiet nan. (MSB=1)
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wire [107:0] qNaN = {4'h1,{104{1'b0}}};
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wire [N*4-1:0] qNaN = {4'h1,{(N-1)*4{1'b0}}};
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// variables
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// variables
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wire [231:0] divo;
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wire [(N+2)*4*2-1:0] divo;
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// Operands
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// Operands
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wire sa, sb; // sign bit
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wire sa, sb; // sign bit
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wire sxa, sxb;
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wire sxa, sxb;
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wire [15:0] xa, xb; // exponent bits
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wire [15:0] xa, xb; // exponent bits
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wire [107:0] siga, sigb;
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wire [N*4-1:0] siga, sigb;
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wire a_dn, b_dn; // a/b is denormalized
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wire a_dn, b_dn; // a/b is denormalized
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wire az, bz;
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wire az, bz;
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wire aInf, bInf;
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wire aInf, bInf;
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wire aNan,bNan;
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wire aNan,bNan;
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wire done1;
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wire done1;
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// Clock #2 to N
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// Clock #2 to N
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// - calculate fraction
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// - calculate fraction
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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wire done3a,done3;
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wire done3a,done3;
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// Perform divide
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// Perform divide
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dfdiv #(108+8) u2 (.clk(clk), .ld(ld1), .a({siga,8'b0}), .b({sigb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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dfdiv #(N+2) u2 (.clk(clk), .ld(ld1), .a({siga,8'b0}), .b({sigb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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wire [7:0] lzcnt_bin = lzcnt[3:0] + (lzcnt[7:4] * 10);
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wire [7:0] lzcnt_bin = lzcnt[3:0] + (lzcnt[7:4] * 10);
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wire [231:0] divo1 = divo[231:0] << ({lzcnt_bin,2'b0}+(FPWID+44));
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wire [(N+2)*4*2-1:0] divo1 = divo[(N+2)*4*2-1:0] << ({lzcnt_bin,2'b0}+(N*4));//WAS FPWID=128?+44
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delay #(.WID(1), .DEP(3)) u3 (.clk(clk), .ce(ce), .i(done1), .o(done3a));
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delay #(.WID(1), .DEP(3)) u3 (.clk(clk), .ce(ce), .i(done1), .o(done3a));
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assign done3 = done1&done3a;
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assign done3 = done1&done3a;
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// Clock #N+1
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// Clock #N+1
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5'b00001: xo <= 1'd0; // underflow
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5'b00001: xo <= 1'd0; // underflow
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default: xo <= ex1; // normal or underflow: passthru neg. exp. for normalization
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default: xo <= ex1; // normal or underflow: passthru neg. exp. for normalization
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endcase
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endcase
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casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
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casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
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8'b1???????: begin mo <= {4'h1,a[107:0],{111{1'b0}}}; st[3] <= 1'b1; end
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8'b1???????: begin mo <= {4'h1,a[N*4-1:0],{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end
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8'b01??????: begin mo <= {4'h1,b[107:0],{111{1'b0}}}; st[3] <= 1'b1; end
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8'b01??????: begin mo <= {4'h1,b[N*4-1:0],{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end
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8'b001?????: begin mo <= {4'h1,qNaN[107:0]|{aInf,1'b0}|{az,bz},{1111{1'b0}}}; st[3] <= 1'b1; end
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8'b001?????: begin mo <= {4'h1,qNaN[N*4-1:0]|{aInf,1'b0}|{az,bz},{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end
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8'b0001????: begin mo <= 224'd0; st[3] <= 1'b0; end // div by inf
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8'b0001????: begin mo <= {(N+1)*4*2-1{1'd0}}; st[3] <= 1'b0; end // div by inf
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8'b00001???: begin mo <= 224'd0; st[3] <= 1'b0; end // div by zero
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8'b00001???: begin mo <= {(N+1)*4*2-1{1'd0}}; st[3] <= 1'b0; end // div by zero
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8'b000001??: begin mo <= 224'd0; st[3] <= 1'b0; end // Inf exponent
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8'b000001??: begin mo <= {(N+1)*4*2-1{1'd0}}; st[3] <= 1'b0; end // Inf exponent
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8'b0000001?: begin mo <= {4'h1,qNaN|`QINFDIV,{111{1'b0}}}; st[3] <= 1'b1; end // infinity / infinity
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8'b0000001?: begin mo <= {4'h1,qNaN|`QINFDIV,{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end // infinity / infinity
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8'b00000001: begin mo <= {4'h1,qNaN|`QZEROZERO,{111{1'b0}}}; st[3] <= 1'b1; end // zero / zero
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8'b00000001: begin mo <= {4'h1,qNaN|`QZEROZERO,{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end // zero / zero
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default: begin mo <= divo1[231:8]; st[3] <= 1'b0; end // plain div
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default: begin mo <= divo1[(N+2)*4*2-1:8]; st[3] <= 1'b0; end // plain div
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endcase
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endcase
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st[0] <= sxo;
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st[0] <= sxo;
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st[1] <= aInf;
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st[1] <= aInf;
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st[2] <= ~(sa ^ sb);
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st[2] <= ~(sa ^ sb);
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end
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end
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endmodule
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endmodule
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module DFPDividenr(rst, clk, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
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module DFPDividenr(rst, clk, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
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parameter N=33;
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input rst;
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input rst;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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input op;
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input op;
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input [127:0] a, b;
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input [N*4+16+4-1:0] a, b;
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output [127:0] o;
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output [N*4+16+4-1:0] o;
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input [2:0] rm;
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input [2:0] rm;
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output sign_exe;
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output sign_exe;
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output done;
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output done;
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output inf;
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output inf;
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output overflow;
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output overflow;
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output underflow;
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output underflow;
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wire [243:0] o1;
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wire [(N+1)*4*2+16+4-1:0] o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire [131:0] fpn0;
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wire [N*4+16+4-1+4:0] fpn0;
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wire done1, done1a;
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wire done1, done1a;
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DFPDivide #(FPWID) u1 (rst, clk, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
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DFPDivide #(.N(N)) u1 (rst, clk, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
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DFPNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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DFPNormalize #(.N(N)) u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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DFPRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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DFPRound #(.N(N)) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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delay #(.WID(1),.DEP(11)) u8(.clk(clk), .ce(ce), .i(done1), .o(done1a));
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delay #(.WID(1),.DEP(11)) u8(.clk(clk), .ce(ce), .i(done1), .o(done1a));
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