URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPDivide96.sv] - Diff between revs 80 and 81

Rev 80	Rev 81
Line 246...	Line 246...
`DFPRound96 #(.N(N)) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );`	`DFPRound96 #(.N(N)) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );`
`delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));`	`delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));`
`delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));`	`delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));`
`delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));`	`delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));`
`delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));`	`delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));`
`ft_delay #(.WID(1),.DEP(11)) u8(.clk(clk), .ce(ce), .i(done1), .o(done1a));`	`ft_delay #(.WID(1),.DEP(14)) u8(.clk(clk), .ce(ce), .i(done1), .o(done1a));`
`assign done = done1&done1a;`	`assign done = done1&done1a;`

`endmodule`	`endmodule`