| Line 132... |
Line 132... |
// Clock #2 to N
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// Clock #2 to N
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// - calculate fraction
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// - calculate fraction
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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wire done3a,done3;
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wire done3a,done3;
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// Perform divide
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// Perform divide
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dfdiv2 #(N+2) u2 (.clk(clk), .ld(ld1), .a({siga,8'b0}), .b({sigb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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dfdiv #(N+2) u2 (.clk(clk), .ld(ld1), .a({siga,8'b0}), .b({sigb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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//wire [7:0] lzcnt_bin = lzcnt[3:0] + (lzcnt[7:4] * 10);
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//wire [7:0] lzcnt_bin = lzcnt[3:0] + (lzcnt[7:4] * 10);
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wire [(N+2)*4*2-1:0] divo1 = divo[(N+2)*4*2-1:0] << ({lzcnt-1,2'b0});//WAS FPWID=128?+44
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wire [(N+2)*4*2-1:0] divo1 = divo[(N+2)*4*2-1:0] << ({lzcnt-1,2'b0});//WAS FPWID=128?+44
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ft_delay #(.WID(1), .DEP(3)) u3 (.clk(clk), .ce(ce), .i(done1), .o(done3a));
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ft_delay #(.WID(1), .DEP(3)) u3 (.clk(clk), .ce(ce), .i(done1), .o(done3a));
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assign done3 = done1&done3a;
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assign done3 = done1&done3a;
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| Line 152... |
Line 152... |
// - also factor in the different decimal position for division
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// - also factor in the different decimal position for division
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reg [13:0] ex1; // sum of exponents
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reg [13:0] ex1; // sum of exponents
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reg qNaNOut;
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reg qNaNOut;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) ex1 <= au.exp - bu.exp + bias - (({lzcnt,2'b00} > N+2) ? lzcnt-(N+2) : 0);
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if (ce) ex1 <= au.exp - bu.exp + bias - ((lzcnt > N+2) ? lzcnt-(N+2) : 0);
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always @(posedge clk)
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always @(posedge clk)
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if (ce) qNaNOut <= (az&bz)|(aInf&bInf);
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if (ce) qNaNOut <= (az&bz)|(aInf&bInf);
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wire over = 1'b0;
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wire over = 1'b0;
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