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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPDivide96.sv] - Diff between revs 82 and 85

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Rev 82 Rev 85
Line 152... Line 152...
// - also factor in the different decimal position for division
// - also factor in the different decimal position for division
reg [13:0] ex1; // sum of exponents
reg [13:0] ex1; // sum of exponents
reg qNaNOut;
reg qNaNOut;
 
 
always @(posedge clk)
always @(posedge clk)
  if (ce) ex1 <= au.exp - bu.exp + bias - ((lzcnt > N+2) ? lzcnt-(N+2) : 0);
  if (ce) ex1 <= au.exp - bu.exp + bias - ((lzcnt >= N) ? lzcnt-N-1 : 0);
 
 
always @(posedge clk)
always @(posedge clk)
  if (ce) qNaNOut <= (az&bz)|(aInf&bInf);
  if (ce) qNaNOut <= (az&bz)|(aInf&bInf);
 
 
wire over = 1'b0;
wire over = 1'b0;

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