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//
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//
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// ============================================================================
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// ============================================================================
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import fp::*;
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import fp::*;
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module DFPMultiply(clk, ce, a, b, o, sign_exe, inf, overflow, underflow);
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//`define DFPMUL_PARALLEL 1'b1
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module DFPMultiply(clk, ce, ld, a, b, o, sign_exe, inf, overflow, underflow, done);
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input [127:0] a, b;
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input [127:0] a, b;
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output [243:0] o;
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output [243:0] o;
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output sign_exe;
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output sign_exe;
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output inf;
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output inf;
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output overflow;
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output overflow;
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output underflow;
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output underflow;
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output done;
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parameter DELAY =
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parameter DELAY =
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(FPWID == 128 ? 17 :
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(FPWID == 128 ? 17 :
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FPWID == 80 ? 17 :
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FPWID == 80 ? 17 :
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FPWID == 64 ? 13 :
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FPWID == 64 ? 13 :
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FPWID == 40 ? 8 :
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FPWID == 40 ? 8 :
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// First clock
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// First clock
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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reg under, over;
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reg under, over;
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reg [15:0] sum_ex;
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reg [15:0] sum_ex, sum_ex1;
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reg sx0;
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reg sx0;
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wire done1;
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DFPDecompose u1a (.i(a), .sgn(sa), .sx(sxa), .exp(xa), .sig(siga), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
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DFPDecompose u1a (.i(a), .sgn(sa), .sx(sxa), .exp(xa), .sig(siga), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
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DFPDecompose u1b (.i(b), .sgn(sb), .sx(sxb), .exp(xb), .sig(sigb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
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DFPDecompose u1b (.i(b), .sgn(sb), .sx(sxb), .exp(xb), .sig(sigb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
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// Compute the sum of the exponents.
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// Compute the sum of the exponents.
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wire [15:0] xapxb, xamxb, xbmxa;
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wire [15:0] xapxb, xamxb, xbmxa;
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wire xapxbc, xamxbc, xbmxac;
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wire xapxbc, xamxbc, xbmxac;
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BCDAddN #(.N(4)) u1c (.ci(1'b0), .a(xa), .b(xb), .o(xapxb), .co(xapxbc));
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BCDAddN #(.N(4)) u1c (.ci(1'b0), .a(xa), .b(xb), .o(xapxb), .co(xapxbc));
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BCDSubN #(.N(4)) u1d (.ci(1'b0), .a(xa), .b(xb), .o(xamxb), .co(xamxbc));
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BCDSubN #(.N(4)) u1d (.ci(1'b0), .a(xa), .b(xb), .o(xamxb), .co(xamxbc));
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BCDSubN #(.N(4)) u1e (.ci(1'b0), .a(xb), .b(xa), .o(xbmxa), .co(xbmxac));
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BCDSubN #(.N(4)) u1e (.ci(1'b0), .a(xb), .b(xa), .o(xbmxa), .co(xbmxac));
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BCDSubN #(.N(5)) u1h (.ci(1'b0), .a(20'h10000), .b(sum_ex1), .o(sum_ex2), .co());
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always @*
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always @*
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case({sxa,sxb})
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case({sxa,sxb})
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2'b11: begin sum_ex <= xapxb; over <= xapxbc; under <= 1'b0; sx0 <= sxa; end
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2'b11: begin sum_ex1 <= xapxb; over <= xapxbc; under <= 1'b0; sx0 <= sxa; end
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2'b01: begin sum_ex <= xbmxa; over <= 1'b0; under <= 1'b0; sx0 <= ~xbmxac; end
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2'b01: begin sum_ex1 <= xbmxa; over <= 1'b0; under <= 1'b0; sx0 <= ~xbmxac; end
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2'b10: begin sum_ex <= xamxb; over <= 1'b0; under <= 1'b0; sx0 <= ~xamxbc; end
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2'b10: begin sum_ex1 <= xamxb; over <= 1'b0; under <= 1'b0; sx0 <= ~xamxbc; end
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2'b00: begin sum_ex <= xapxb; over <= 1'b0; under <= xapxbc; sx0 <= sxa; end
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2'b00: begin sum_ex1 <= xapxb; over <= 1'b0; under <= xapxbc; sx0 <= sxa; end
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endcase
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endcase
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// Take nine's complement if exponent sign changed.
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always @*
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if ((sxa^sxb)) begin
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if ((sxa & xamxbc) || (sxb & xbmxac))
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sum_ex <= sum_ex2;
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else
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sum_ex <= sum_ex1;
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end
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else
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sum_ex <= sum_ex1;
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wire [255:0] sigoo;
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wire [255:0] sigoo;
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`ifdef DFPMUL_PARALLEL
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BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));
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BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));
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`else
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dfmul u1g
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(
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.clk(clk),
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.ld(ld),
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.a(siga),
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.b(sigb),
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.p(sigoo),
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.done(done1)
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);
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`endif
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always @(posedge clk)
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always @(posedge clk)
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if (ce) sig1 <= sigoo[215:0];
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if (ce) sig1 <= sigoo[215:0];
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// Status
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// Status
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// - correct xponent and mantissa for exceptional conditions
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// - correct xponent and mantissa for exceptional conditions
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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wire so1, sx1;
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wire so1, sx1;
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reg [3:0] st;
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reg [3:0] st;
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wire done1a;
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delay #(.WID(1),.DEP(1)) u8 (.clk(clk), .ce(ce), .i(~(sa ^ sb)), .o(so1) );// two clock delay!
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delay #(.WID(1),.DEP(1)) u8 (.clk(clk), .ce(ce), .i(~(sa ^ sb)), .o(so1) );// two clock delay!
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delay #(.WID(1),.DEP(1)) u9 (.clk(clk), .ce(ce), .i(sx0), .o(sx1) );// two clock delay!
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delay #(.WID(1),.DEP(1)) u9 (.clk(clk), .ce(ce), .i(sx0), .o(sx1) );// two clock delay!
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always @(posedge clk)
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always @(posedge clk)
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delay #(.WID(1),.DEP(DELAY+1)) u10 (.clk(clk), .ce(ce), .i(sa & sb), .o(sign_exe) );
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delay #(.WID(1),.DEP(DELAY+1)) u10 (.clk(clk), .ce(ce), .i(sa & sb), .o(sign_exe) );
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delay1 u11 (.clk(clk), .ce(ce), .i(over1), .o(overflow) );
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delay1 u11 (.clk(clk), .ce(ce), .i(over1), .o(overflow) );
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delay1 u12 (.clk(clk), .ce(ce), .i(over1), .o(inf) );
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delay1 u12 (.clk(clk), .ce(ce), .i(over1), .o(inf) );
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delay1 u13 (.clk(clk), .ce(ce), .i(under1), .o(underflow) );
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delay1 u13 (.clk(clk), .ce(ce), .i(under1), .o(underflow) );
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delay #(.WID(1),.DEP(3)) u18 (.clk(clk), .ce(ce), .i(done1), .o(done1a) );
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assign o = {st,xo1,mo1,8'h00};
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assign o = {st,xo1,mo1,8'h00};
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assign done = done1&done1a;
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endmodule
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endmodule
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// Multiplier with normalization and rounding.
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// Multiplier with normalization and rounding.
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module DFPMultiplynr(clk, ce, a, b, o, rm, sign_exe, inf, overflow, underflow);
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module DFPMultiplynr(clk, ce, ld, a, b, o, rm, sign_exe, inf, overflow, underflow, done);
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input [127:0] a, b;
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input [127:0] a, b;
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output [127:0] o;
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output [127:0] o;
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input [2:0] rm;
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input [2:0] rm;
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output sign_exe;
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output sign_exe;
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output inf;
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output inf;
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output overflow;
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output overflow;
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output underflow;
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output underflow;
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output done;
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wire done1, done1a;
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wire [243:0] o1;
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wire [243:0] o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire [131:0] fpn0;
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wire [131:0] fpn0;
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DFPMultiply u1 (clk, ce, a, b, o1, sign_exe1, inf1, overflow1, underflow1);
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DFPMultiply u1 (clk, ce, ld, a, b, o1, sign_exe1, inf1, overflow1, underflow1, done1);
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DFPNormalize u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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DFPNormalize u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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DFPRound u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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DFPRound u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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delay #(.WID(1),.DEP(11)) u10 (.clk(clk), .ce(ce), .i(done1), .o(done1a) );
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assign done = done1 & done1a;
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endmodule
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endmodule
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