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import fp::*;
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import fp::*;
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//`define DFPMUL_PARALLEL 1'b1
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//`define DFPMUL_PARALLEL 1'b1
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module DFPMultiply(clk, ce, ld, a, b, o, sign_exe, inf, overflow, underflow, done);
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module DFPMultiply(clk, ce, ld, a, b, o, sign_exe, inf, overflow, underflow, done);
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parameter N=33;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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input [127:0] a, b;
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input [N*4+16+4-1:0] a, b;
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output [243:0] o;
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output [(N+1)*4*2+16+4-1:0] o;
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output sign_exe;
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output sign_exe;
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output inf;
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output inf;
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output overflow;
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output overflow;
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output underflow;
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output underflow;
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output done;
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output done;
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FPWID == 40 ? 8 :
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FPWID == 40 ? 8 :
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FPWID == 32 ? 2 :
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FPWID == 32 ? 2 :
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FPWID == 16 ? 2 : 2);
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FPWID == 16 ? 2 : 2);
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reg [15:0] xo1; // extra bit for sign
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reg [15:0] xo1; // extra bit for sign
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reg [215:0] mo1;
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reg [N*4*2-1:0] mo1;
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// constants
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// constants
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wire [15:0] infXp = 16'h9999; // infinite / NaN - all ones
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wire [15:0] infXp = 16'h9999; // infinite / NaN - all ones
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// The following is the value for an exponent of zero, with the offset
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// The following is the value for an exponent of zero, with the offset
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// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
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// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
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// The following is a template for a quiet nan. (MSB=1)
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// The following is a template for a quiet nan. (MSB=1)
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wire [107:0] qNaN = {4'h1,{104{1'b0}}};
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wire [N*4-1:0] qNaN = {4'h1,{104{1'b0}}};
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// variables
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// variables
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reg [215:0] sig1;
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reg [N*4*2-1:0] sig1;
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wire [15:0] ex2;
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wire [15:0] ex2;
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// Decompose the operands
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// Decompose the operands
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wire sa, sb; // sign bit
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wire sa, sb; // sign bit
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wire [15:0] xa, xb; // exponent bits
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wire [15:0] xa, xb; // exponent bits
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wire sxa, sxb;
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wire sxa, sxb;
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wire [107:0] siga, sigb;
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wire [N*4-1:0] siga, sigb;
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wire a_dn, b_dn; // a/b is denormalized
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wire a_dn, b_dn; // a/b is denormalized
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wire aNan, bNan, aNan1, bNan1;
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wire aNan, bNan, aNan1, bNan1;
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wire az, bz;
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wire az, bz;
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wire aInf, bInf, aInf1, bInf1;
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wire aInf, bInf, aInf1, bInf1;
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sum_ex <= sum_ex1;
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sum_ex <= sum_ex1;
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end
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end
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else
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else
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sum_ex <= sum_ex1;
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sum_ex <= sum_ex1;
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wire [255:0] sigoo;
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wire [N*4*2-1:0] sigoo;
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`ifdef DFPMUL_PARALLEL
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`ifdef DFPMUL_PARALLEL
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BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));
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BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));
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`else
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`else
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dfmul u1g
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dfmul #(.N(N)) u1g
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(
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(
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.clk(clk),
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.clk(clk),
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.ld(ld),
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.ld(ld),
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.a(siga),
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.a(siga),
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.b(sigb),
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.b(sigb),
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.done(done1)
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.done(done1)
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);
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);
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`endif
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`endif
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always @(posedge clk)
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always @(posedge clk)
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if (ce) sig1 <= sigoo[215:0];
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if (ce) sig1 <= sigoo[N*4*2-1:0];
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// Status
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// Status
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wire under1, over1;
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wire under1, over1;
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delay #(.WID(16),.DEP(DELAY)) u3 (.clk(clk), .ce(ce), .i(sum_ex), .o(ex2) );
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delay #(.WID(16),.DEP(DELAY)) u3 (.clk(clk), .ce(ce), .i(sum_ex), .o(ex2) );
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delay #(.WID(1),.DEP(DELAY)) u6 (.clk(clk), .ce(ce), .i(under), .o(under1) );
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delay #(.WID(1),.DEP(DELAY)) u6 (.clk(clk), .ce(ce), .i(under), .o(under1) );
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delay #(.WID(1),.DEP(DELAY)) u7 (.clk(clk), .ce(ce), .i(over), .o(over1) );
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delay #(.WID(1),.DEP(DELAY)) u7 (.clk(clk), .ce(ce), .i(over), .o(over1) );
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// determine when a NaN is output
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// determine when a NaN is output
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wire qNaNOut;
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wire qNaNOut;
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wire [127:0] a1,b1;
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wire [N*4+16+4-1:0] a1,b1;
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delay #(.WID(1),.DEP(DELAY)) u5 (.clk(clk), .ce(ce), .i((aInf&bz)|(bInf&az)), .o(qNaNOut) );
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delay #(.WID(1),.DEP(DELAY)) u5 (.clk(clk), .ce(ce), .i((aInf&bz)|(bInf&az)), .o(qNaNOut) );
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delay #(.WID(1),.DEP(DELAY)) u14 (.clk(clk), .ce(ce), .i(aNan), .o(aNan1) );
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delay #(.WID(1),.DEP(DELAY)) u14 (.clk(clk), .ce(ce), .i(aNan), .o(aNan1) );
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delay #(.WID(1),.DEP(DELAY)) u15 (.clk(clk), .ce(ce), .i(bNan), .o(bNan1) );
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delay #(.WID(1),.DEP(DELAY)) u15 (.clk(clk), .ce(ce), .i(bNan), .o(bNan1) );
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delay #(.WID(128),.DEP(DELAY)) u16 (.clk(clk), .ce(ce), .i(a), .o(a1) );
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delay #(.WID(N*4+16+4),.DEP(DELAY)) u16 (.clk(clk), .ce(ce), .i(a), .o(a1) );
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delay #(.WID(128),.DEP(DELAY)) u17 (.clk(clk), .ce(ce), .i(b), .o(b1) );
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delay #(.WID(N*4+16+4),.DEP(DELAY)) u17 (.clk(clk), .ce(ce), .i(b), .o(b1) );
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// Second clock
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// Second clock
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// - correct xponent and mantissa for exceptional conditions
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// - correct xponent and mantissa for exceptional conditions
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// Force mantissa to zero when underflow or zero exponent when not supporting denormals.
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// Force mantissa to zero when underflow or zero exponent when not supporting denormals.
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1|under1})
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casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1|under1})
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6'b1?????: mo1 = {4'h1,a1[103:0],108'b0};
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6'b1?????: mo1 = {4'h1,a1[N*4-4-1:0],{N*4{1'b0}}};
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6'b01????: mo1 = {4'h1,b1[103:0],108'b0};
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6'b01????: mo1 = {4'h1,b1[N*4-4-1:0],{N*4{1'b0}}};
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6'b001???: mo1 = {4'h1,qNaN|3'd4,108'b0}; // multiply inf * zero
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6'b001???: mo1 = {4'h1,qNaN|3'd4,{N*4{1'b0}}}; // multiply inf * zero
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6'b0001??: mo1 = 0; // mul inf's
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6'b0001??: mo1 = 0; // mul inf's
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6'b00001?: mo1 = 0; // mul inf's
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6'b00001?: mo1 = 0; // mul inf's
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6'b000001: mo1 = 0; // mul overflow
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6'b000001: mo1 = 0; // mul overflow
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default: mo1 = sig1;
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default: mo1 = sig1;
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endcase
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endcase
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// Multiplier with normalization and rounding.
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// Multiplier with normalization and rounding.
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module DFPMultiplynr(clk, ce, ld, a, b, o, rm, sign_exe, inf, overflow, underflow, done);
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module DFPMultiplynr(clk, ce, ld, a, b, o, rm, sign_exe, inf, overflow, underflow, done);
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parameter N=33;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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input [127:0] a, b;
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input [N*4+16+4-1:0] a, b;
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output [127:0] o;
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output [N*4+16+4-1:0] o;
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input [2:0] rm;
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input [2:0] rm;
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output sign_exe;
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output sign_exe;
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output inf;
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output inf;
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output overflow;
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output overflow;
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output underflow;
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output underflow;
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output done;
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output done;
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wire done1, done1a;
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wire done1, done1a;
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wire [243:0] o1;
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wire [(N+1)*4*2+16+4-1:0] o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire [131:0] fpn0;
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wire [N*4+16+4-1+4:0] fpn0;
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DFPMultiply u1 (clk, ce, ld, a, b, o1, sign_exe1, inf1, overflow1, underflow1, done1);
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DFPMultiply u1 (clk, ce, ld, a, b, o1, sign_exe1, inf1, overflow1, underflow1, done1);
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DFPNormalize u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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DFPNormalize u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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DFPRound u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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DFPRound u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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