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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPMultiply.sv] - Diff between revs 54 and 55

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Rev 54 Rev 55
Line 59... Line 59...
import fp::*;
import fp::*;
 
 
//`define DFPMUL_PARALLEL       1'b1
//`define DFPMUL_PARALLEL       1'b1
 
 
module DFPMultiply(clk, ce, ld, a, b, o, sign_exe, inf, overflow, underflow, done);
module DFPMultiply(clk, ce, ld, a, b, o, sign_exe, inf, overflow, underflow, done);
 
parameter N=33;
input clk;
input clk;
input ce;
input ce;
input ld;
input ld;
input  [127:0] a, b;
input  [N*4+16+4-1:0] a, b;
output [243:0] o;
output [(N+1)*4*2+16+4-1:0] o;
output sign_exe;
output sign_exe;
output inf;
output inf;
output overflow;
output overflow;
output underflow;
output underflow;
output done;
output done;
Line 78... Line 79...
  FPWID == 40 ? 8 :
  FPWID == 40 ? 8 :
  FPWID == 32 ? 2 :
  FPWID == 32 ? 2 :
  FPWID == 16 ? 2 : 2);
  FPWID == 16 ? 2 : 2);
 
 
reg [15:0] xo1;         // extra bit for sign
reg [15:0] xo1;         // extra bit for sign
reg [215:0] mo1;
reg [N*4*2-1:0] mo1;
 
 
// constants
// constants
wire [15:0] infXp = 16'h9999;   // infinite / NaN - all ones
wire [15:0] infXp = 16'h9999;   // infinite / NaN - all ones
// The following is the value for an exponent of zero, with the offset
// The following is the value for an exponent of zero, with the offset
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
// The following is a template for a quiet nan. (MSB=1)
// The following is a template for a quiet nan. (MSB=1)
wire [107:0] qNaN  = {4'h1,{104{1'b0}}};
wire [N*4-1:0] qNaN  = {4'h1,{104{1'b0}}};
 
 
// variables
// variables
reg [215:0] sig1;
reg [N*4*2-1:0] sig1;
wire [15:0] ex2;
wire [15:0] ex2;
 
 
// Decompose the operands
// Decompose the operands
wire sa, sb;                    // sign bit
wire sa, sb;                    // sign bit
wire [15:0] xa, xb;     // exponent bits
wire [15:0] xa, xb;     // exponent bits
wire sxa, sxb;
wire sxa, sxb;
wire [107:0] siga, sigb;
wire [N*4-1:0] siga, sigb;
wire a_dn, b_dn;                        // a/b is denormalized
wire a_dn, b_dn;                        // a/b is denormalized
wire aNan, bNan, aNan1, bNan1;
wire aNan, bNan, aNan1, bNan1;
wire az, bz;
wire az, bz;
wire aInf, bInf, aInf1, bInf1;
wire aInf, bInf, aInf1, bInf1;
 
 
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                        sum_ex <= sum_ex1;
                        sum_ex <= sum_ex1;
        end
        end
        else
        else
                sum_ex <= sum_ex1;
                sum_ex <= sum_ex1;
 
 
wire [255:0] sigoo;
wire [N*4*2-1:0] sigoo;
`ifdef DFPMUL_PARALLEL
`ifdef DFPMUL_PARALLEL
BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));
BCDMul32 u1f (.a({20'h0,siga}),.b({20'h0,sigb}),.o(sigoo));
`else
`else
dfmul u1g
dfmul #(.N(N)) u1g
(
(
        .clk(clk),
        .clk(clk),
        .ld(ld),
        .ld(ld),
        .a(siga),
        .a(siga),
        .b(sigb),
        .b(sigb),
Line 166... Line 167...
        .done(done1)
        .done(done1)
);
);
`endif
`endif
 
 
always @(posedge clk)
always @(posedge clk)
  if (ce) sig1 <= sigoo[215:0];
  if (ce) sig1 <= sigoo[N*4*2-1:0];
 
 
// Status
// Status
wire under1, over1;
wire under1, over1;
 
 
delay #(.WID(16),.DEP(DELAY)) u3 (.clk(clk), .ce(ce), .i(sum_ex), .o(ex2) );
delay #(.WID(16),.DEP(DELAY)) u3 (.clk(clk), .ce(ce), .i(sum_ex), .o(ex2) );
Line 179... Line 180...
delay #(.WID(1),.DEP(DELAY)) u6  (.clk(clk), .ce(ce), .i(under), .o(under1) );
delay #(.WID(1),.DEP(DELAY)) u6  (.clk(clk), .ce(ce), .i(under), .o(under1) );
delay #(.WID(1),.DEP(DELAY)) u7  (.clk(clk), .ce(ce), .i(over), .o(over1) );
delay #(.WID(1),.DEP(DELAY)) u7  (.clk(clk), .ce(ce), .i(over), .o(over1) );
 
 
// determine when a NaN is output
// determine when a NaN is output
wire qNaNOut;
wire qNaNOut;
wire [127:0] a1,b1;
wire [N*4+16+4-1:0] a1,b1;
delay #(.WID(1),.DEP(DELAY)) u5 (.clk(clk), .ce(ce), .i((aInf&bz)|(bInf&az)), .o(qNaNOut) );
delay #(.WID(1),.DEP(DELAY)) u5 (.clk(clk), .ce(ce), .i((aInf&bz)|(bInf&az)), .o(qNaNOut) );
delay #(.WID(1),.DEP(DELAY)) u14 (.clk(clk), .ce(ce), .i(aNan), .o(aNan1) );
delay #(.WID(1),.DEP(DELAY)) u14 (.clk(clk), .ce(ce), .i(aNan), .o(aNan1) );
delay #(.WID(1),.DEP(DELAY)) u15 (.clk(clk), .ce(ce), .i(bNan), .o(bNan1) );
delay #(.WID(1),.DEP(DELAY)) u15 (.clk(clk), .ce(ce), .i(bNan), .o(bNan1) );
delay #(.WID(128),.DEP(DELAY))  u16 (.clk(clk), .ce(ce), .i(a), .o(a1) );
delay #(.WID(N*4+16+4),.DEP(DELAY))  u16 (.clk(clk), .ce(ce), .i(a), .o(a1) );
delay #(.WID(128),.DEP(DELAY))  u17 (.clk(clk), .ce(ce), .i(b), .o(b1) );
delay #(.WID(N*4+16+4),.DEP(DELAY))  u17 (.clk(clk), .ce(ce), .i(b), .o(b1) );
 
 
// -----------------------------------------------------------
// -----------------------------------------------------------
// Second clock
// Second clock
// - correct xponent and mantissa for exceptional conditions
// - correct xponent and mantissa for exceptional conditions
// -----------------------------------------------------------
// -----------------------------------------------------------
Line 213... Line 214...
 
 
// Force mantissa to zero when underflow or zero exponent when not supporting denormals.
// Force mantissa to zero when underflow or zero exponent when not supporting denormals.
always @(posedge clk)
always @(posedge clk)
        if (ce)
        if (ce)
                casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1|under1})
                casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1|under1})
                6'b1?????:  mo1 = {4'h1,a1[103:0],108'b0};
                6'b1?????:  mo1 = {4'h1,a1[N*4-4-1:0],{N*4{1'b0}}};
    6'b01????:  mo1 = {4'h1,b1[103:0],108'b0};
    6'b01????:  mo1 = {4'h1,b1[N*4-4-1:0],{N*4{1'b0}}};
                6'b001???:      mo1 = {4'h1,qNaN|3'd4,108'b0};  // multiply inf * zero
                6'b001???:      mo1 = {4'h1,qNaN|3'd4,{N*4{1'b0}}};     // multiply inf * zero
                6'b0001??:      mo1 = 0;        // mul inf's
                6'b0001??:      mo1 = 0;        // mul inf's
                6'b00001?:      mo1 = 0;        // mul inf's
                6'b00001?:      mo1 = 0;        // mul inf's
                6'b000001:      mo1 = 0;        // mul overflow
                6'b000001:      mo1 = 0;        // mul overflow
                default:        mo1 = sig1;
                default:        mo1 = sig1;
                endcase
                endcase
Line 245... Line 246...
 
 
 
 
// Multiplier with normalization and rounding.
// Multiplier with normalization and rounding.
 
 
module DFPMultiplynr(clk, ce, ld, a, b, o, rm, sign_exe, inf, overflow, underflow, done);
module DFPMultiplynr(clk, ce, ld, a, b, o, rm, sign_exe, inf, overflow, underflow, done);
 
parameter N=33;
input clk;
input clk;
input ce;
input ce;
input ld;
input ld;
input  [127:0] a, b;
input  [N*4+16+4-1:0] a, b;
output [127:0] o;
output [N*4+16+4-1:0] o;
input [2:0] rm;
input [2:0] rm;
output sign_exe;
output sign_exe;
output inf;
output inf;
output overflow;
output overflow;
output underflow;
output underflow;
output done;
output done;
 
 
wire done1, done1a;
wire done1, done1a;
wire [243:0] o1;
wire [(N+1)*4*2+16+4-1:0] o1;
wire sign_exe1, inf1, overflow1, underflow1;
wire sign_exe1, inf1, overflow1, underflow1;
wire [131:0] fpn0;
wire [N*4+16+4-1+4:0] fpn0;
 
 
DFPMultiply  u1 (clk, ce, ld, a, b, o1, sign_exe1, inf1, overflow1, underflow1, done1);
DFPMultiply  u1 (clk, ce, ld, a, b, o1, sign_exe1, inf1, overflow1, underflow1, done1);
DFPNormalize u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
DFPNormalize u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
DFPRound     u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
DFPRound     u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));

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