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// ============================================================================
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// ============================================================================
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import fp::*;
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import fp::*;
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module DFPNormalize(clk, ce, i, o, under_i, under_o, inexact_o);
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module DFPNormalize(clk, ce, i, o, under_i, under_o, inexact_o);
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parameter N=33;
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input clk;
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input clk;
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input ce;
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input ce;
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input [243:0] i; // expanded format input
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input [(N+1)*4*2+16+4-1:0] i; // expanded format input
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output [131:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit
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output [N*4+16+4-1+4:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit
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input under_i;
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input under_i;
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output under_o;
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output under_o;
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output inexact_o;
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output inexact_o;
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integer n;
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integer n;
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| Line 58... |
Line 59... |
reg sx0;
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reg sx0;
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reg nan0;
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reg nan0;
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reg inf0;
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reg inf0;
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always @*
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always @*
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xo0 <= i[239:224];
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xo0 <= i[(N+1)*4*2+15:(N+1)*4*2];
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always @*
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always @*
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so0 <= i[242]; // sign doesn't change
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so0 <= i[(N+1)*4*2+16+4-2]; // sign doesn't change
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always @*
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always @*
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sx0 <= i[240];
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sx0 <= i[(N+1)*4*2+16+4-4];
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always @*
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always @*
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nan0 <= i[243];
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nan0 <= i[(N+1)*4*2+16+4-1];
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always @*
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always @*
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inf0 <= i[241] || xo0==16'h9999 && i[220];
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inf0 <= i[(N+1)*4*2+16+4-3] || xo0==16'h9999 && i[(N+1)*4*2-4];
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock #1
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// Clock #1
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// - Capture exponent information
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// - Capture exponent information
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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reg xInf1a, xInf1b, xInf1c;
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reg xInf1a, xInf1b, xInf1c;
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wire [243:0] i1;
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wire [(N+1)*4*2+16+4-1:0] i1;
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delay #(.WID(244),.DEP(1)) u11 (.clk(clk), .ce(ce), .i(i), .o(i1));
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delay #(.WID((N+2)*4*2+16+4),.DEP(1)) u11 (.clk(clk), .ce(ce), .i(i), .o(i1));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xInf1a <= xo0==16'h9999 & !under_i;
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if (ce) xInf1a <= xo0==16'h9999 & !under_i;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xInf1b <= xo0==16'h9998 & !under_i;
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if (ce) xInf1b <= xo0==16'h9998 & !under_i;
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delay #(.WID(1),.DEP(1)) u22 (.clk(clk), .ce(ce), .i(xInf1b), .o(xInf2b));
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delay #(.WID(1),.DEP(1)) u22 (.clk(clk), .ce(ce), .i(xInf1b), .o(xInf2b));
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delay #(.WID(16),.DEP(2)) u23 (.clk(clk), .ce(ce), .i(xo0), .o(xo2));
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delay #(.WID(16),.DEP(2)) u23 (.clk(clk), .ce(ce), .i(xo0), .o(xo2));
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delay #(.WID(1),.DEP(2)) u24 (.clk(clk), .ce(ce), .i(under_i), .o(under2));
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delay #(.WID(1),.DEP(2)) u24 (.clk(clk), .ce(ce), .i(under_i), .o(under2));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) incExpByOne2 <= !xInf1a & i1[220];
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if (ce) incExpByOne2 <= !xInf1a & i1[(N+1)*4*2-4];
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock #3
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// Clock #3
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// - increment exponent
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// - increment exponent
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// - detect a zero mantissa
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// - detect a zero mantissa
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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wire incExpByOne3;
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wire incExpByOne3;
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wire [243:0] i3;
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wire [(N+1)*4*2+16+4-1:0] i3;
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reg [15:0] xo3;
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reg [15:0] xo3;
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reg zeroMan3;
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reg zeroMan3;
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delay #(.WID(1),.DEP(1)) u32 (.clk(clk), .ce(ce), .i(incExpByOne2), .o(incExpByOne3));
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delay #(.WID(1),.DEP(1)) u32 (.clk(clk), .ce(ce), .i(incExpByOne2), .o(incExpByOne3));
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delay #(.WID(244),.DEP(3)) u33 (.clk(clk), .ce(ce), .i(i[243:0]), .o(i3));
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delay #(.WID((N+1)*4*2+16+4),.DEP(3)) u33 (.clk(clk), .ce(ce), .i(i[(N+3)*4*2+16+4-1:0]), .o(i3));
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wire [15:0] xo2a;
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wire [15:0] xo2a;
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BCDAddN #(.N(4)) ubcdan1
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BCDAddN #(.N(4)) ubcdan1
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(
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(
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.ci(1'b0),
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.ci(1'b0),
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// - If infinity is reached then set the mantissa to zero
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// - If infinity is reached then set the mantissa to zero
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// shift mantissa left to reduce to a single whole digit
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// shift mantissa left to reduce to a single whole digit
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// - create sticky bit
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// - create sticky bit
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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reg [115:0] mo4;
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reg [(N+2)*4-1:0] mo4;
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reg inexact4;
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reg inexact4;
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always @(posedge clk)
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always @(posedge clk)
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if(ce)
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if(ce)
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casez({zeroMan3,incExpByOne3})
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casez({zeroMan3,incExpByOne3})
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2'b1?: mo4 <= 1'd0;
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2'b1?: mo4 <= 1'd0;
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2'b01: mo4 <= {i3[223:112],3'b0,|i3[111:0]};
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2'b01: mo4 <= {i3[(N+1)*4*2-1:(N+1)*4],3'b0,|i3[(N+1)*4-1:0]};
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default: mo4 <= {i3[219:108],3'b0,|i3[107:0]};
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default: mo4 <= {i3[(N+1)*4*2-1-4:N*4],3'b0,|i3[N*4-1:0]};
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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if(ce)
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if(ce)
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casez({zeroMan3,incExpByOne3})
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casez({zeroMan3,incExpByOne3})
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2'b1?: inexact4 <= 1'd0;
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2'b1?: inexact4 <= 1'd0;
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2'b01: inexact4 <= |i3[111:0];
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2'b01: inexact4 <= |i3[(N+1)*4-1:0];
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default: inexact4 <= |i3[107:0];
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default: inexact4 <= |i3[N*4-1:0];
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endcase
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endcase
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock edge #5
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// Clock edge #5
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// - count leading zeros
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// - count leading zeros
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Line 210... |
reg got_one;
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reg got_one;
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always @*
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always @*
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begin
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begin
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got_one = 1'b0;
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got_one = 1'b0;
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lzc = 8'h00;
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lzc = 8'h00;
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for (n = 115; n >= 0; n = n - 4) begin
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for (n = (N+2)*4-1; n >= 0; n = n - 4) begin
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if (!got_one) begin
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if (!got_one) begin
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if (mo4[n]|mo4[n-1]|mo4[n-2]|mo4[n-3])
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if (mo4[n]|mo4[n-1]|mo4[n-2]|mo4[n-3])
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got_one = 1'b1;
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got_one = 1'b1;
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else
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else
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lzc = lzc + 1'b1;
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lzc = lzc + 1'b1;
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| Line 223... |
Line 224... |
always @(posedge clk)
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always @(posedge clk)
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if (ce) leadingZeros5 <= lzc;
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if (ce) leadingZeros5 <= lzc;
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`else
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`else
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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casez(mo4[111:103])
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casez(mo4[(N+1)*4-1:(N-1)*4-1])
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8'h00000000: leadingZeros5 <= 8'd2;
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8'h00000000: leadingZeros5 <= 8'd2;
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8'h0000????: leadingZeros5 <= 8'd1;
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8'h0000????: leadingZeros5 <= 8'd1;
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default: leadingZeros5 <= 8'd0;
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default: leadingZeros5 <= 8'd0;
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endcase
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endcase
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`endif
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`endif
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| Line 247... |
Line 248... |
reg [7:0] lshiftAmt6;
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reg [7:0] lshiftAmt6;
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reg [7:0] rshiftAmt6;
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reg [7:0] rshiftAmt6;
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wire rightOrLeft6; // 0=left,1=right
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wire rightOrLeft6; // 0=left,1=right
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wire xInf6;
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wire xInf6;
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wire [15:0] xo6;
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wire [15:0] xo6;
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wire [115:0] mo6;
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wire [(N+2)*4-1:0] mo6;
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wire zeroMan6;
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wire zeroMan6;
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vtdl #(1) u61 (.clk(clk), .ce(ce), .a(4'd5), .d(under_i), .q(rightOrLeft6) );
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vtdl #(1) u61 (.clk(clk), .ce(ce), .a(4'd5), .d(under_i), .q(rightOrLeft6) );
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delay #(.WID(16),.DEP(1)) u62 (.clk(clk), .ce(ce), .i(xo5), .o(xo6));
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delay #(.WID(16),.DEP(1)) u62 (.clk(clk), .ce(ce), .i(xo5), .o(xo6));
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delay #(.WID(116),.DEP(2)) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) );
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delay #(.WID((N+2)*4),.DEP(2)) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) );
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delay #(.WID(1),.DEP(1)) u64 (.clk(clk), .ce(ce), .i(xInf5), .o(xInf6) );
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delay #(.WID(1),.DEP(1)) u64 (.clk(clk), .ce(ce), .i(xInf5), .o(xInf6) );
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delay #(.WID(1),.DEP(3)) u65 (.clk(clk), .ce(ce), .i(zeroMan3), .o(zeroMan6));
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delay #(.WID(1),.DEP(3)) u65 (.clk(clk), .ce(ce), .i(zeroMan3), .o(zeroMan6));
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delay #(.WID(1),.DEP(5)) u66 (.clk(clk), .ce(ce), .i(sx0), .o(sx5) );
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delay #(.WID(1),.DEP(5)) u66 (.clk(clk), .ce(ce), .i(sx0), .o(sx5) );
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wire [13:0] xo5d = xo5[3:0] + xo5[7:4] * 10 + xo5[11:8] * 100 + xo5[15:12] * 1000;
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wire [13:0] xo5d = xo5[3:0] + xo5[7:4] * 10 + xo5[11:8] * 100 + xo5[15:12] * 1000;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) lshiftAmt6 <= {leadingZeros5 > xo5d ? xo5d : leadingZeros5,2'b0};
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if (ce) lshiftAmt6 <= {leadingZeros5 > xo5d ? xo5d : leadingZeros5,2'b0};
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always @(posedge clk)
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always @(posedge clk)
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if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : sx5 ? 1'd0 : xo5d > 14'd24 ? 8'd96 : {xo5d[5:0],2'b00}; // xo2 is negative !
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if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : sx5 ? 1'd0 : xo5d > N ? N*4 : {xo5d[5:0],2'b00}; // xo2 is negative !
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock edge #7
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// Clock edge #7
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// - figure exponent
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// - figure exponent
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// - shift mantissa
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// - shift mantissa
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// - figure sticky bit
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// - figure sticky bit
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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reg [15:0] xo7;
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reg [15:0] xo7;
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wire rightOrLeft7;
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wire rightOrLeft7;
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reg [115:0] mo7l, mo7r;
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reg [(N+2)*4-1:0] mo7l, mo7r;
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reg St6,St7;
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reg St6,St7;
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delay #(.WID(1),.DEP(1)) u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
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delay #(.WID(1),.DEP(1)) u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
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wire [11:0] lshftAmtBCD;
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wire [11:0] lshftAmtBCD;
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wire [15:0] xo7d;
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wire [15:0] xo7d;
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| Line 306... |
Line 307... |
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// The sticky bit is set if the bits shifted out on a right shift are set.
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// The sticky bit is set if the bits shifted out on a right shift are set.
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always @*
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always @*
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begin
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begin
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St6 = 1'b0;
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St6 = 1'b0;
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for (n = 0; n < 116; n = n + 1)
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for (n = 0; n < (N+2)*4; n = n + 1)
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if (n <= rshiftAmt6 + 1) St6 = St6|mo6[n];
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if (n <= rshiftAmt6 + 1) St6 = St6|mo6[n];
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if (ce) St7 <= St6;
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if (ce) St7 <= St6;
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| Line 319... |
Line 320... |
// - select mantissa
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// - select mantissa
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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wire so,sxo,nano,info;
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wire so,sxo,nano,info;
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wire [15:0] xo;
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wire [15:0] xo;
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reg [115:0] mo;
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reg [(N+2)*4-1:0] mo;
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vtdl #(1) u81 (.clk(clk), .ce(ce), .a(4'd7), .d(so0), .q(so) );
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vtdl #(1) u81 (.clk(clk), .ce(ce), .a(4'd7), .d(so0), .q(so) );
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delay #(.WID(16),.DEP(1)) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo));
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delay #(.WID(16),.DEP(1)) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo));
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vtdl #(.WID(1)) u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
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vtdl #(.WID(1)) u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
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delay #(.WID(1),.DEP(1)) u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
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delay #(.WID(1),.DEP(1)) u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
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vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd7), .d(sx0), .q(sxo) );
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vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd7), .d(sx0), .q(sxo) );
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| Line 331... |
Line 332... |
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd7), .d(inf0), .q(info) );
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vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd7), .d(inf0), .q(info) );
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always @(posedge clk)
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always @(posedge clk)
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if (ce) mo <= rightOrLeft7 ? mo7r|{St7,4'b0} : mo7l;
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if (ce) mo <= rightOrLeft7 ? mo7r|{St7,4'b0} : mo7l;
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assign o = {nano,so,info,sxo,xo,mo[115:4]};
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assign o = {nano,so,info,sxo,xo,mo[(N+2)*4-1:4]};
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endmodule
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endmodule
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