URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPNormalize96.sv] - Diff between revs 75 and 78

Rev 75	Rev 78
Line 273...	Line 273...
`wire rightOrLeft7;`	`wire rightOrLeft7;`
`reg [(N+2)*4-1:0] mo7l, mo7r;`	`reg [(N+2)*4-1:0] mo7l, mo7r;`
`reg St6,St7;`	`reg St6,St7;`
`ft_delay #(.WID(1),.DEP(1)) u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));`	`ft_delay #(.WID(1),.DEP(1)) u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));`

`wire [11:0] xo7d = xo6 - lshiftAmt6;`

`always_ff @(posedge clk)`	`always_ff @(posedge clk)`
`if (ce)`	`if (ce)`
`xo7 <= zeroMan6 ? xo6 :`	`casez({zeroMan6,xInf6,rightOrLeft6})`
`xInf6 ? xo6 : // an infinite exponent is either a NaN or infinity; no need to change`	`3'b1??: xo7 <= xo6;`
`rightOrLeft6 ? 1'd0 : // on a right shift, the exponent was negative, it's being made to zero`	`3'b01?: xo7 <= xo6; // an infinite exponent is either a NaN or infinity; no need to change`
`xo7d; // on a left shift, the exponent can't be decremented below zero`	`3'b001: xo7 <= 'd0; // on a right shift, the exponent was negative, it's being made to zero`
	`default: xo7 <= xo6 - lshiftAmt6[7:2]; // lshiftAmt6 is a multiple of four (whole digit)`
	`endcase`

`always_ff @(posedge clk)`	`always_ff @(posedge clk)`
`if (ce) mo7r <= mo6 >> rshiftAmt6;`	`if (ce) mo7r <= mo6 >> rshiftAmt6;`
`always_ff @(posedge clk)`	`always_ff @(posedge clk)`
`if (ce) mo7l <= mo6 << lshiftAmt6;`	`if (ce) mo7l <= mo6 << lshiftAmt6;`