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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPPack.sv] - Diff between revs 57 and 75

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Rev 57 Rev 75
Line 42... Line 42...
output DFP128 o;
output DFP128 o;
 
 
wire [109:0] enc_sig;
wire [109:0] enc_sig;
DPDEncodeN #(.N(11)) u1 (i.sig[131:0], enc_sig);
DPDEncodeN #(.N(11)) u1 (i.sig[131:0], enc_sig);
 
 
always @*
always_comb
begin
begin
        // sign
        // sign
        o.sign <= i.sign;
        o.sign <= i.sign;
        // combo
        // combo
        if (i.qnan|i.snan)
        if (i.qnan|i.snan)
Line 66... Line 66...
        o.sigc <= enc_sig;
        o.sigc <= enc_sig;
end
end
 
 
endmodule
endmodule
 
 
 
module DFPPack96(i, o);
 
input DFP96U i;
 
output DFP96 o;
 
 
 
wire [79:0] enc_sig;
 
DPDEncodeN #(.N(8)) u1 (i.sig[95:0], enc_sig);
 
 
 
always_comb
 
begin
 
        // sign
 
        o.sign <= i.sign;
 
        // combo
 
        if (i.qnan|i.snan)
 
                o.combo <= 5'b11111;
 
        else if (i.infinity)
 
                o.combo <= 5'b11110;
 
        else
 
                o.combo <= i.sig[99:96] > 4'h7 ? {2'b11,i.exp[11:10],i.sig[96]} : {i.exp[11:10],i.sig[98:96]};
 
        // exponent continuation
 
        if (i.qnan)
 
                o.expc <= {1'b0,i.exp[8:0]};
 
        else if (i.snan)
 
                o.expc <= {1'b1,i.exp[8:0]};
 
        else
 
                o.expc <= i.exp[9:0];
 
        // significand continuation
 
        o.sigc <= enc_sig;
 
end
 
 
 
endmodule
module DFPPack64(i, o);
module DFPPack64(i, o);
input DFP64U i;
input DFP64U i;
output DFP64 o;
output DFP64 o;
 
 
wire [49:0] enc_sig;
wire [49:0] enc_sig;
DPDEncodeN #(.N(5)) u1 (i.sig[59:0], enc_sig);
DPDEncodeN #(.N(5)) u1 (i.sig[59:0], enc_sig);
 
 
always @*
always_comb
begin
begin
        // sign
        // sign
        o.sign <= i.sign;
        o.sign <= i.sign;
        // combo
        // combo
        if (i.qnan|i.snan)
        if (i.qnan|i.snan)

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