| Line 46... |
Line 46... |
`else
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`else
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`define PIPE_ADV (posedge clk)
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`define PIPE_ADV (posedge clk)
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`endif
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`endif
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module DFPRound(clk, ce, rm, i, o);
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module DFPRound(clk, ce, rm, i, o);
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parameter N=33;
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input clk;
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input clk;
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input ce;
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input ce;
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input [2:0] rm; // rounding mode
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input [2:0] rm; // rounding mode
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input [131:0] i; // intermediate format input
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input [N*4+16+4+4-1:0] i; // intermediate format input
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output [127:0] o; // rounded output
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output [N*4+16+4-1:0] o; // rounded output
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parameter ROUND_CEILING = 3'd0;
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parameter ROUND_CEILING = 3'd0;
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parameter ROUND_FLOOR = 3'd1;
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parameter ROUND_FLOOR = 3'd1;
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parameter ROUND_HALF_UP = 3'd2;
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parameter ROUND_HALF_UP = 3'd2;
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parameter ROUND_HALF_EVEN = 3'd3;
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parameter ROUND_HALF_EVEN = 3'd3;
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| Line 62... |
Line 63... |
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//------------------------------------------------------------
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//------------------------------------------------------------
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// variables
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// variables
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wire [3:0] so;
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wire [3:0] so;
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wire [15:0] xo;
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wire [15:0] xo;
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reg [107:0] mo;
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reg [N*4-1:0] mo;
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reg [15:0] xo1;
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reg [15:0] xo1;
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reg [107:0] mo1;
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reg [N*4-1:0] mo1;
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wire xInf = i[127:112]==16'h9999;
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wire xInf = i[N*4+16+4-1:(N+1)*4]==16'h9999;
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wire so0 = i[130];
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wire so0 = i[N*4+16+4-2];
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assign o = {so,xo,mo};
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assign o = {so,xo,mo};
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wire [3:0] l = i[7:4];
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wire [3:0] l = i[7:4];
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wire [3:0] r = i[3:0];
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wire [3:0] r = i[3:0];
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| Line 80... |
Line 81... |
// Clock #1
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// Clock #1
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// - determine round amount (add 1 or 0)
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// - determine round amount (add 1 or 0)
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//------------------------------------------------------------
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//------------------------------------------------------------
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always @`PIPE_ADV
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always @`PIPE_ADV
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if (ce) xo1 <= i[127:112];
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if (ce) xo1 <= i[N*4+16+4-1:(N+1)*4];
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always @`PIPE_ADV
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always @`PIPE_ADV
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if (ce) mo1 <= i[111:4];
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if (ce) mo1 <= i[(N+1)*4-1:4];
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// Compute the round bit
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// Compute the round bit
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// Infinities and NaNs are not rounded!
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// Infinities and NaNs are not rounded!
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always @`PIPE_ADV
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always @`PIPE_ADV
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if (ce)
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if (ce)
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| Line 107... |
Line 108... |
// round the number, check for carry
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// round the number, check for carry
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// note: inf. exponent checked above (if the exponent was infinite already, then no rounding occurs as rnd = 0)
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// note: inf. exponent checked above (if the exponent was infinite already, then no rounding occurs as rnd = 0)
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// note: exponent increments if there is a carry (can only increment to infinity)
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// note: exponent increments if there is a carry (can only increment to infinity)
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//------------------------------------------------------------
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//------------------------------------------------------------
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wire [123:0] rounded1;
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wire [N*4+16+4-1-4:0] rounded1;
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wire co1;
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wire co1;
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BCDAddN #(.N(31)) ubcdan1
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BCDAddN #(.N(N+4)) ubcdan1
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(
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(
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.ci(1'b0),
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.ci(1'b0),
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.a({xo1,mo1}),
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.a({xo1,mo1}),
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.b({123'd0,rnd}),
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.b({{N*4+16+4-1-4{1'd0}},rnd}),
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.o(rounded1),
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.o(rounded1),
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.co(co1)
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.co(co1)
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);
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);
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reg [123:0] rounded2;
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reg [N*4+16+4-1-4:0] rounded2;
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reg carry2;
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reg carry2;
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reg rnd2;
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reg rnd2;
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reg dn2;
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reg dn2;
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wire [15:0] xo2;
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wire [15:0] xo2;
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always @`PIPE_ADV
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always @`PIPE_ADV
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| Line 133... |
Line 134... |
if (ce) carry2 <= co1;
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if (ce) carry2 <= co1;
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always @`PIPE_ADV
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always @`PIPE_ADV
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if (ce) rnd2 <= rnd;
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if (ce) rnd2 <= rnd;
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always @`PIPE_ADV
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always @`PIPE_ADV
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if (ce) dn2 <= !(|xo1);
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if (ce) dn2 <= !(|xo1);
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assign xo2 = rounded2[123:108];
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assign xo2 = rounded2[N*4+16+4-1-4:N*4];
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|
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Clock #3
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// Clock #3
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// - shift mantissa if required.
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// - shift mantissa if required.
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//------------------------------------------------------------
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//------------------------------------------------------------
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`ifdef MIN_LATENCY
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`ifdef MIN_LATENCY
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assign so = i[131:128];
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assign so = i[N*4+16+4+3:N*4+16+4];
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assign xo = xo2;
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assign xo = xo2;
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`else
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`else
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delay3 #(4) u21 (.clk(clk), .ce(ce), .i(i[131:128]), .o(so));
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delay3 #(4) u21 (.clk(clk), .ce(ce), .i(i[N*4+16+4+3:N*4+16+4]), .o(so));
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delay1 #(16) u22 (.clk(clk), .ce(ce), .i(xo2), .o(xo));
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delay1 #(16) u22 (.clk(clk), .ce(ce), .i(xo2), .o(xo));
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`endif
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`endif
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always @`PIPE_ADV
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always @`PIPE_ADV
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if (ce)
|
if (ce)
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casez({rnd2,xo2==16'h9999,carry2,dn2})
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casez({rnd2,xo2==16'h9999,carry2,dn2})
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4'b0??0: mo <= mo1[107:0]; // not rounding, not denormalized
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4'b0??0: mo <= mo1[N*4-1:0]; // not rounding, not denormalized
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4'b0??1: mo <= mo1[107:0]; // not rounding, denormalized
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4'b0??1: mo <= mo1[N*4-1:0]; // not rounding, denormalized
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4'b1000: mo <= rounded2[107: 0]; // exponent didn't change, number was normalized
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4'b1000: mo <= rounded2[N*4-1: 0]; // exponent didn't change, number was normalized
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4'b1001: mo <= rounded2[107: 0]; // exponent didn't change, but number was denormalized
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4'b1001: mo <= rounded2[N*4-1: 0]; // exponent didn't change, but number was denormalized
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4'b1010: mo <= {4'h1,rounded2[107: 4]}; // exponent incremented (new MSD generated), number was normalized
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4'b1010: mo <= {4'h1,rounded2[N*4-1: 4]}; // exponent incremented (new MSD generated), number was normalized
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4'b1011: mo <= rounded2[107:0]; // exponent incremented (new MSB generated), number was denormalized, number became normalized
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4'b1011: mo <= rounded2[N*4-1:0]; // exponent incremented (new MSB generated), number was denormalized, number became normalized
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4'b11??: mo <= 108'd0; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite
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4'b11??: mo <= {N*4{1'd0}}; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite
|
endcase
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endcase
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endmodule
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endmodule
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