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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2021 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// DFPRound128.sv
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// DFPRound128.sv
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parameter N=34;
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parameter N=34;
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input clk;
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input clk;
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input ce;
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input ce;
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input [2:0] rm; // rounding mode
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input [2:0] rm; // rounding mode
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input DFP128UN i; // intermediate format input
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input DFP128UN i; // intermediate format input
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output DFP128U o; // rounded output
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output DFP128 o; // packed rounded output
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parameter ROUND_CEILING = 3'd0;
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parameter ROUND_CEILING = 3'd0;
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parameter ROUND_FLOOR = 3'd1;
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parameter ROUND_FLOOR = 3'd1;
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parameter ROUND_HALF_UP = 3'd2;
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parameter ROUND_HALF_UP = 3'd2;
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parameter ROUND_HALF_EVEN = 3'd3;
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parameter ROUND_HALF_EVEN = 3'd3;
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reg [N*4-1:0] mo;
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reg [N*4-1:0] mo;
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reg [13:0] xo1;
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reg [13:0] xo1;
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reg [N*4-1:0] mo1;
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reg [N*4-1:0] mo1;
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wire xInf = i.exp==14'h3FFF;
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wire xInf = i.exp==14'h3FFF;
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wire so0 = i.sign;
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wire so0 = i.sign;
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assign o = {so,xo,mo};
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assign o.nan = nano;
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assign o.qnan = qnano;
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assign o.snan = snano;
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assign o.infinity = infinity;
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assign o.sign = so;
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assign o.exp = xo;
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assign o.sig = mo;
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wire [3:0] l = i.sig[7:4];
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wire [3:0] l = i.sig[7:4];
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wire [3:0] r = i.sig[3:0];
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wire [3:0] r = i.sig[3:0];
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reg rnd;
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reg rnd;
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4'b1010: mo <= {4'h1,rounded2[N*4-1: 4]}; // exponent incremented (new MSD generated), number was normalized
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4'b1010: mo <= {4'h1,rounded2[N*4-1: 4]}; // exponent incremented (new MSD generated), number was normalized
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4'b1011: mo <= rounded2[N*4-1:0]; // exponent incremented (new MSB generated), number was denormalized, number became normalized
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4'b1011: mo <= rounded2[N*4-1:0]; // exponent incremented (new MSB generated), number was denormalized, number became normalized
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4'b11??: mo <= {N*4{1'd0}}; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite
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4'b11??: mo <= {N*4{1'd0}}; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite
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endcase
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endcase
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//------------------------------------------------------------
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// Clock #4
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// - Pack output
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//------------------------------------------------------------
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DFP128U o1;
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DFP128 o2;
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assign o1.nan = nano;
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assign o1.qnan = qnano;
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assign o1.snan = snano;
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assign o1.infinity = infinity;
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assign o1.sign = so;
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assign o1.exp = xo;
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assign o1.sig = mo;
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DFPPack128 u41 (o1, o2);
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always_ff @(posedge clk)
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if (ce) o <= o2;
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endmodule
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endmodule
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